diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2018-06-24 12:02:59 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2018-08-10 16:44:17 +0000 |
| commit | 940bb4ea422c77126b22b1cb293c5ef794ed071c (patch) | |
| tree | 72698a77cabeb3c5ec007df8c798940dcb2bc8ab /src/mainboard/gigabyte/ga-h61m-s2pv | |
| parent | dfc30130e94e97d42389e4b7ef7e2227df99cdf7 (diff) | |
mb/gigabyte/ga-{h61m-s2pv,b75m-d3h,b75m-d3v}: Clean up mainboard code
I ported ga-h61m-s2pv based on the two Gigabyte b75m boards.
Based on another mainboard's code review comments, this patch
improves the code quality of these three similar boards.
ga-h61m-s2pv is tested and confirmed to be working, but I cannot
say the same regarding the other two mainboards as I do not have them.
Change-Id: Ib7747cceb5ba56f791677204cdc4c54c129c70c3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/27211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/gigabyte/ga-h61m-s2pv')
| -rw-r--r-- | src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb | 8 | ||||
| -rw-r--r-- | src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl | 6 | ||||
| -rw-r--r-- | src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c | 6 |
3 files changed, 7 insertions, 13 deletions
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb index 9102b82086..7ff7fbea09 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb @@ -14,14 +14,8 @@ ## chip northbridge/intel/sandybridge - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" - register "gfx.link_frequency_270_mhz" = "0" register "gfx.ndid" = "3" - register "gfx.use_spread_spectrum_clock" = "0" - register "gpu_dp_b_hotplug" = "4" - register "gpu_dp_c_hotplug" = "4" - register "gpu_dp_d_hotplug" = "4" - register "gpu_panel_port_select" = "0" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" device cpu_cluster 0x0 on chip cpu/intel/socket_LGA1155 device lapic 0x0 on diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl b/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl index d5719cc58c..71d238db44 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl @@ -38,9 +38,9 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> - #include <southbridge/intel/bd82x6x/acpi/pch.asl> + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> } } } diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c b/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c index 3e63721bd3..f1cd176641 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c @@ -57,11 +57,11 @@ void mainboard_early_init(int s3resume) void mainboard_config_superio(void) { - /* Enable serial port and flip some magic bits */ - + /* Enable serial port */ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - ite_reg_write(SUPERIO_GPIO, 0xEF, 0x7E); // magic + /* Disable SIO WDT which kicks in DualBIOS */ + ite_reg_write(SUPERIO_GPIO, 0xEF, 0x7E); } void mainboard_get_spd(spd_raw_data *spd, bool id_only) |