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authorJohn Zhao <john.zhao@intel.com>2021-01-01 14:19:36 -0800
committerPatrick Georgi <pgeorgi@google.com>2021-01-08 08:22:47 +0000
commit4ead6b33671bba5f67f1cb0d6df5979b47e4ccc0 (patch)
tree3f9f760468fcc7d2af07f592b97b1139176e56c3 /src/mainboard/gigabyte/ga-g41m-es2l/Kconfig.name
parent81a4c344e7015666b047a05fc0ecb90ad9013d64 (diff)
soc/intel/tigerlake: Enable USB2 port reset message on Type-C ports
USB3 is in CPU and USB2 in PCH on Tigerlake. Cross die messaging is implemented between CPU and PCH through the IOSF SB bridge. a PCH xHCI USB2 port reset event issued by the xHCI driver shall trigger a message upstream to CPU to wake it from the low power state which allows a USB3 device that downgraded to USB2 to upgrade back to USB3. BUG=b:176575892 TEST=Built and booted to kernel on Voxel board. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I672f30a117980bc10bd71e9b77c5fa76286b9f5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/49052 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/gigabyte/ga-g41m-es2l/Kconfig.name')
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