mb/gigabyte/ga-945gcm-s2l: add mainboard

Startpoint was Intel d945gclf, which has same chipset and
Gigabyte ga-g41m-es2l which has same Superio.

What works and is tested:
* PCI slot;
* PCIe x16 slot with GPU (RADEON HD 2600 XT) and ADD2 DVI card;
* onboard VGA output (only textmode implemented) with native graphic init;
* 533, 800, 1067MHz FSB CPU (1333MHz is unsupported by the chipset);
* serial output during and after boot.

What does not work:
* resume from suspend (does not work for d945gclf either).

Quirks:
* The Realtek ethernet card requires a reset which currently also
  hardcodes a MAC adress.

This board was only tested with the SeaBIOS payload due to flash size
constraints (512KB) and with GNU/Linux.

Change-Id: I0ff9f193105facc1b276a791790e27eb4c275085
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17033
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

1 files changed, 217 insertions, 0 deletions

diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
new file mode 100644
index 0000000000..d83ab745b1
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
@@ -0,0 +1,217 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2016 Arthur Heymans arthur@aheymans.xyz
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+// __PRE_RAM__ means: use "unsigned" for device, not a struct.
+
+#include <stdint.h>
+#include <string.h>
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <lib.h>
+#include <arch/acpi.h>
+#include <cbmem.h>
+#include <superio/ite/it8718f/it8718f.h>
+#include <superio/ite/common/ite.h>
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
+#include <cpu/x86/bist.h>
+#include <cpu/intel/romstage.h>
+#include <northbridge/intel/i945/i945.h>
+#include <northbridge/intel/i945/raminit.h>
+#include <southbridge/intel/i82801gx/i82801gx.h>
+
+#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
+#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO)
+#define EC_DEV PNP_DEV(0x2e, IT8718F_EC)
+#define SUPERIO_DEV PNP_DEV(0x2e, 0)
+
+void setup_ich7_gpios(void)
+{
+	/* TODO: This is highly board specific and should be moved */
+	printk(BIOS_DEBUG, " GPIOS...");
+	/* General Registers */
+	outl(0x1f15f7c1, DEFAULT_GPIOBASE + 0x00);	/* GPIO_USE_SEL */
+	outl(0xe0e8ffc3, DEFAULT_GPIOBASE + 0x04);	/* GP_IO_SEL */
+	outl(0xe2fefc03, DEFAULT_GPIOBASE + 0x0c);	/* GP_LVL */
+	/* Output Control Registers */
+	outl(0x00400000, DEFAULT_GPIOBASE + 0x18);	/* GPO_BLINK */
+	/* Input Control Registers */
+	outl(0x000039ff, DEFAULT_GPIOBASE + 0x2c);	/* GPI_INV */
+	outl(0x000000c7, DEFAULT_GPIOBASE + 0x30);	/* GPIO_USE_SEL2 */
+	outl(0x000000f0, DEFAULT_GPIOBASE + 0x34);	/* GP_IO_SEL2 */
+	outl(0x000000f2, DEFAULT_GPIOBASE + 0x38);	/* GP_LVL2 */
+}
+
+static void setup_sio(void)
+{
+	/* Set default GPIOs on superio */
+	ite_reg_write(GPIO_DEV, 0x25, 0x40);
+	ite_reg_write(GPIO_DEV, 0x26, 0x3f);
+	ite_reg_write(GPIO_DEV, 0x28, 0x41);
+	ite_reg_write(GPIO_DEV, 0x29, 0x88);
+	ite_reg_write(GPIO_DEV, 0x2c, 0x1c);
+	ite_reg_write(GPIO_DEV, 0x62, 0x08);
+	ite_reg_write(GPIO_DEV, 0x72, 0x00);
+	ite_reg_write(GPIO_DEV, 0x73, 0x38);
+	ite_reg_write(GPIO_DEV, 0xb1, 0x01);
+	ite_reg_write(GPIO_DEV, 0xb8, 0x80);
+	ite_reg_write(GPIO_DEV, 0xbb, 0x40);
+	ite_reg_write(GPIO_DEV, 0xc0, 0x00);
+	ite_reg_write(GPIO_DEV, 0xc3, 0x00);
+	ite_reg_write(GPIO_DEV, 0xc8, 0x00);
+	ite_reg_write(GPIO_DEV, 0xcb, 0x00);
+	ite_reg_write(GPIO_DEV, 0xf6, 0x26);
+	ite_reg_write(GPIO_DEV, 0xfc, 0x4a);
+
+	ite_reg_write(EC_DEV, 0x70, 0x00); // Don't use IRQ9
+	ite_reg_write(EC_DEV, 0x30, 0xff); // Enable
+}
+
+static void ich7_enable_lpc(void)
+{
+	// Enable Serial IRQ
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
+	// Set COM1/COM2 decode range
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);
+	// Enable COM1
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340d);
+	// Enable SuperIO Power Management Events
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0801);
+}
+
+static void rcba_config(void)
+{
+	/* Enable IOAPIC */
+	RCBA8(0x31ff) = 0x03;
+
+	/* Disable unused devices */
+	RCBA32(0x3418) = 0x003c0061;
+
+	/* Enable PCIe Root Port Clock Gate */
+	RCBA32(0x341c) = 0x00000001;
+}
+
+static void early_ich7_init(void)
+{
+	uint8_t reg8;
+	uint32_t reg32;
+
+	// program secondary mlt XXX byte?
+	pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
+
+	// reset rtc power status
+	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
+	reg8 &= ~(1 << 2);
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
+
+	// usb transient disconnect
+	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
+	reg8 |= (3 << 0);
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
+
+	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
+	reg32 |= (1 << 29) | (1 << 17);
+	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
+
+	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
+	reg32 |= (1 << 31) | (1 << 27);
+	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
+
+	RCBA32(0x0088) = 0x0011d000;
+	RCBA16(0x01fc) = 0x060f;
+	RCBA32(0x01f4) = 0x86000040;
+	RCBA32(0x0214) = 0x10030509;
+	RCBA32(0x0218) = 0x00020504;
+	RCBA8(0x0220) = 0xc5;
+	reg32 = RCBA32(0x3410);
+	reg32 |= (1 << 6);
+	RCBA32(0x3410) = reg32;
+	reg32 = RCBA32(0x3430);
+	reg32 &= ~(3 << 0);
+	reg32 |= (1 << 0);
+	RCBA32(0x3430) = reg32;
+	RCBA32(0x3418) |= (1 << 0);
+	RCBA16(0x0200) = 0x2008;
+	RCBA8(0x2027) = 0x0d;
+	RCBA16(0x3e08) |= (1 << 7);
+	RCBA16(0x3e48) |= (1 << 7);
+	RCBA32(0x3e0e) |= (1 << 7);
+	RCBA32(0x3e4e) |= (1 << 7);
+
+	// next step only on ich7m b0 and later:
+	reg32 = RCBA32(0x2034);
+	reg32 &= ~(0x0f << 16);
+	reg32 |= (5 << 16);
+	RCBA32(0x2034) = reg32;
+}
+
+void mainboard_romstage_entry(unsigned long bist)
+{
+	int s3resume = 0, boot_mode = 0;
+
+	if (bist == 0)
+		enable_lapic();
+
+	ich7_enable_lpc();
+	/* Enable SuperIO PM */
+	setup_sio();
+	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+
+	/* Disable SIO reboot */
+	ite_reg_write(GPIO_DEV, 0xEF, 0x7E);
+
+	/* Set up the console */
+	console_init();
+
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
+	if (MCHBAR16(SSKPD) == 0xCAFE) {
+		printk(BIOS_DEBUG, "soft reset detected.\n");
+		boot_mode = 1;
+	}
+
+	/* Perform some early chipset initialization required
+	 * before RAM initialization can work
+	 */
+	i945_early_initialization();
+
+	s3resume = southbridge_detect_s3_resume();
+
+	/* Enable SPD ROMs and DDR-II DRAM */
+	enable_smbus();
+
+#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
+	dump_spd_registers();
+#endif
+	sdram_initialize(s3resume ? 2 : boot_mode, NULL);
+
+	/* Perform some initialization that must run before stage2 */
+	early_ich7_init();
+
+	/* This should probably go away. Until now it is required
+	 * and mainboard specific
+	 */
+	rcba_config();
+
+	/* Chipset Errata! */
+	fixup_i945_errata();
+
+	/* Initialize the internal PCIe links before we go into stage2 */
+	i945_late_initialization(s3resume);
+}