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authorArthur Heymans <arthur@aheymans.xyz>2019-01-04 14:23:54 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-01-09 09:56:06 +0000
commit4513020064cc4765e723f6f3cc2b8a45a0dc6545 (patch)
treee9b31b8b64518a62f6a7885a1de54171471c918b /src/mainboard/getac
parent907bd5d44e574227baa1f5b3c00b31b8dc351096 (diff)
cpu/intel: Use the common code to initialize the romstage timestamps
The initial timestamps are now pushed on the stack when entering the romstage C code. Tested on Asus P5QC. Change-Id: I88e972caafff5c53d8e68e85415f920c7341b92d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/getac')
-rw-r--r--src/mainboard/getac/p470/romstage.c5
1 files changed, 0 insertions, 5 deletions
diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index 820a333184..471977fd9d 100644
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -29,7 +29,6 @@
#include <northbridge/intel/i945/i945.h>
#include <northbridge/intel/i945/raminit.h>
#include <southbridge/intel/i82801gx/i82801gx.h>
-#include <timestamp.h>
#include "option_table.h"
static void setup_special_ich7_gpios(void)
@@ -170,7 +169,6 @@ static void rcba_config(void)
/* Enable PCIe Root Port Clock Gate */
// RCBA32(0x341c) = 0x00000001;
-
/* This should probably go into the ACPI enable trap */
/* Set up I/O Trap #0 for 0xfe00 (SMIC) */
RCBA32(0x1e84) = 0x00020001;
@@ -238,9 +236,6 @@ void mainboard_romstage_entry(unsigned long bist)
{
int s3resume = 0;
- timestamp_init(timestamp_get());
- timestamp_add_now(TS_START_ROMSTAGE);
-
if (bist == 0)
enable_lapic();