From 4513020064cc4765e723f6f3cc2b8a45a0dc6545 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Fri, 4 Jan 2019 14:23:54 +0100 Subject: cpu/intel: Use the common code to initialize the romstage timestamps MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The initial timestamps are now pushed on the stack when entering the romstage C code. Tested on Asus P5QC. Change-Id: I88e972caafff5c53d8e68e85415f920c7341b92d Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/30670 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/mainboard/getac/p470/romstage.c | 5 ----- 1 file changed, 5 deletions(-) (limited to 'src/mainboard/getac') diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index 820a333184..471977fd9d 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -29,7 +29,6 @@ #include #include #include -#include #include "option_table.h" static void setup_special_ich7_gpios(void) @@ -170,7 +169,6 @@ static void rcba_config(void) /* Enable PCIe Root Port Clock Gate */ // RCBA32(0x341c) = 0x00000001; - /* This should probably go into the ACPI enable trap */ /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ RCBA32(0x1e84) = 0x00020001; @@ -238,9 +236,6 @@ void mainboard_romstage_entry(unsigned long bist) { int s3resume = 0; - timestamp_init(timestamp_get()); - timestamp_add_now(TS_START_ROMSTAGE); - if (bist == 0) enable_lapic(); -- cgit v1.2.3