diff options
author | Arthur Heymans <arthur@aheymans.xyz> | 2018-12-15 21:38:39 +0100 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-10 12:17:10 +0000 |
commit | f3e50fc68186fbfa93f77d05f182bf0435e745ab (patch) | |
tree | 12fd4e95d9ceab386dda329cb31f1f79786a77d0 /src/mainboard/foxconn/g41s-k/romstage.c | |
parent | 13f58e47ed995a73b2ae57c25b98afed84675783 (diff) |
mb/foxconn/g41s-k: Add g41m variant
Was tested with the following:
- 2 DIMM slots
- USB
- Ethernet NIC
- automatic fan control
- Libgfxinit with VGA, DVI (HDMI slot unpopulated)
- PS2 Keyboard
- SATA
- PEG
- S3 resume
What does not work:
- Using the second DIMM slot on a channel
G41 can only handle 2 ranks per channel and on this mainboard 1 rank
per DIMM slot. Supporting this would require too much raminit rework
and is not worth it (at least for me)
Change-Id: I67784038ef929f561b82365f00db70a69c024321
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/foxconn/g41s-k/romstage.c')
-rw-r--r-- | src/mainboard/foxconn/g41s-k/romstage.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c index 9ce9c65c5a..7c1402ac44 100644 --- a/src/mainboard/foxconn/g41s-k/romstage.c +++ b/src/mainboard/foxconn/g41s-k/romstage.c @@ -72,7 +72,7 @@ static void ich7_enable_lpc(void) { pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010); pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN | - COMB_LPC_EN | COMA_LPC_EN); + FDD_LPC_EN | COMB_LPC_EN | COMA_LPC_EN); /* Decode 64 bytes at 0x0a00 to LPC for Super I/O EC and GPIO. */ pci_write_config32(LPC_DEV, GEN1_DEC, 0x003c0a01); @@ -81,7 +81,13 @@ static void ich7_enable_lpc(void) void mainboard_romstage_entry(unsigned long bist) { // ch0 ch1 +#if IS_ENABLED(CONFIG_BOARD_FOXCONN_G41S_K) const u8 spd_addrmap[4] = { 0x50, 0, 0, 0 }; +#else + /* TODO adapt raminit such that other slots can be used + * for single rank dimms */ + const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; +#endif u8 boot_path = 0; u8 s3_resume; |