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authorFelix Singer <felixsinger@posteo.net>2024-06-23 03:56:43 +0200
committerFelix Singer <felixsinger@posteo.net>2024-06-24 14:22:46 +0000
commit0c1daa59b902364d26f13290dff0e44bda839539 (patch)
treeb9d4edc690126b00001714f6cea64a7f41f500cb /src/mainboard/facebook
parent1a77d1e437c7dc4efd8ab665ccf1ed9d18ba835d (diff)
skl mainboards/dt: Drop SsicPortEnable setting if disabled
The attributes are initialized with 0 and thus setting them to 0 makes them superfluous. Remove them. Change-Id: Ic16d568c38d708da27efa7229e23019e71c0019b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/facebook')
-rw-r--r--src/mainboard/facebook/monolith/devicetree.cb2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb
index fdb59c9fcf..bf634c513d 100644
--- a/src/mainboard/facebook/monolith/devicetree.cb
+++ b/src/mainboard/facebook/monolith/devicetree.cb
@@ -197,8 +197,6 @@ chip soc/intel/skylake
[3] = USB3_PORT_DEFAULT(OC_SKIP), /* USB-C Port 1 */
}"
- register "SsicPortEnable" = "0"
-
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoDisabled,