soc/intel/cmn/pch/lockdown: Implement LPC lock down configuration

This patch implements a helper function to perform LPC registers lock
down configuration.

BUG=b:211954778
TEST=Able to build and boot google/redrix to OS. Verified LPC PCI
configuration register offset 0xDC bits BILD and LE are set.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3e49b783e5db0ff40238e6e9259e48a4ecca66f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>

0 files changed, 0 insertions, 0 deletions