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authorDavid Milosevic <David.Milosevic@9elements.com>2023-11-16 05:11:18 +0100
committerLean Sheng Tan <sheng.tan@9elements.com>2024-06-08 20:41:14 +0000
commitad83eb1ee6bb833783c4b870c86413978fb5d4ba (patch)
tree34effa2a8c4d42be4b5b06dba8ad0a7b78ef8778 /src/mainboard/emulation/qemu-sbsa/bootblock.c
parent91cda2af74b4142bf459f7416b8f997c7d981e13 (diff)
mainboard/emulation/qemu-sbsa: Add qemu-sbsa board
Add coreboot support for qemu's sbsa-ref (Server Base System Architecture) machine (-m sbsa-ref). The qemu-sbsa coreboot port runs on EL2 and is the payload of the EL3 firmware (Arm Trusted Firmware). Note that, coreboot expects a pointer to the FDT in x0. Make sure to configure TF-A to handoff the FDT pointer. Example qemu commandline: qemu-system-aarch64 -nographic -m 2048 -M sbsa-ref \ -pflash <path/to/TFA.fd> \ -pflash <path/to/coreboot.rom> The Documentation can be found here: Documentation/mainboard/emulation/qemu-sbsa.md Change-Id: Iacc9aaf065e0d153336cbef9a9b5b46a9eb24a53 Signed-off-by: David Milosevic <David.Milosevic@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/mainboard/emulation/qemu-sbsa/bootblock.c')
-rw-r--r--src/mainboard/emulation/qemu-sbsa/bootblock.c22
1 files changed, 22 insertions, 0 deletions
diff --git a/src/mainboard/emulation/qemu-sbsa/bootblock.c b/src/mainboard/emulation/qemu-sbsa/bootblock.c
new file mode 100644
index 0000000000..b38df6ec71
--- /dev/null
+++ b/src/mainboard/emulation/qemu-sbsa/bootblock.c
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/mmu.h>
+#include <bootblock_common.h>
+#include <symbols.h>
+
+void bootblock_mainboard_init(void)
+{
+ mmu_init();
+
+ /* Everything below DRAM is device memory */
+ mmu_config_range((void *)0, (uintptr_t)_dram, MA_DEV | MA_RW);
+ /* Set a dummy value for DRAM. ramstage should update the mapping. */
+ mmu_config_range(_dram, ((size_t) CONFIG_DRAM_SIZE_MB) * MiB, MA_MEM | MA_RW);
+
+ mmu_config_range(_ttb, REGION_SIZE(ttb), MA_MEM | MA_S | MA_RW);
+ mmu_config_range(_bootblock, REGION_SIZE(bootblock), MA_MEM | MA_S | MA_RW);
+ mmu_config_range(_ramstage, REGION_SIZE(ramstage), MA_MEM | MA_S | MA_RW);
+ mmu_config_range((void *)CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH,
+ MA_DEV | MA_RW);
+ mmu_enable();
+}