diff options
| author | Patrick Rudolph <siro@das-labor.org> | 2018-11-11 12:50:51 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-12 15:57:34 +0000 |
| commit | 1af89237094246216c6f60d77d74690a39907999 (patch) | |
| tree | 20c369514e4a340ed33199c0eb8c95adfa577c94 /src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc | |
| parent | 7665aefb0ad216ee76307193b849834eac7b1f88 (diff) | |
mb/emulation/qemu-i440fx|q35: Switch to C_ENVIRONMENT_BOOTBLOCK
Useful for testing stuff in C_ENVIRONMENT_BOOTBLOCK, like
VBOOT with separate verstage.
Changes:
* Use symbols to set up CAR and STACK
* Zero CAR area
* Move BIST failure checking to cpu folder
* Rename functions where necessary
Tested:
* qemu-2.11.2 machine pc
* qemu-2.11.2 machine q35
Test result:
* BIST error reporting is still working.
* Console starts in bootblock
* SeaBios 1.11.2 as payload is still working
Change-Id: Ibf341002c36d868b9b44c8b37381fa78ae5c4381
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/29578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc')
| -rw-r--r-- | src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc | 64 |
1 files changed, 0 insertions, 64 deletions
diff --git a/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc b/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc deleted file mode 100644 index d36341c78b..0000000000 --- a/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com> - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cpu/x86/mtrr.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/post_code.h> - -#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1) - - /* Save the BIST result. */ - movl %eax, %ebp - -cache_as_ram: - post_code(0x20) - /* - * Nothing to do here on qemu, RAM works just fine without any - * initialization. - */ - - post_code(0x21) - /* - * Set up the stack pointer, use top of real mode (640k) memory. - * This value also keeps the copy_and_run stack out of the way - * of big ramstages. The ramstage will load its own %esp so - * there is no harm in using this value. - */ - movl $0xa0000, %eax - movl %eax, %esp - - /* Restore the BIST result. */ - movl %ebp, %eax - movl %esp, %ebp - pushl %eax - -before_romstage: - post_code(0x29) - /* Call romstage.c main function. */ - call romstage_main - - post_code(0x30) - -__main: - post_code(POST_PREPARE_RAMSTAGE) - cld /* Clear direction flag. */ - - call copy_and_run - -.Lhlt: - post_code(POST_DEAD_CODE) - hlt - jmp .Lhlt |