diff options
| author | Mate Kukri <kukri.mate@gmail.com> | 2024-03-31 11:49:58 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-04-12 16:17:08 +0000 |
| commit | 1ce416eda19fcafccaba8ad56a1fa28ec22f4b60 (patch) | |
| tree | a5e4c4da980013a7c8606da36a0e69c6e60dd0e5 /src/mainboard/dell/optiplex_9020/overridetree_mt.cb | |
| parent | 4bbec0c6916ba272410c0f4541e32c2f91a7affc (diff) | |
mb/dell/optiplex_9020: Fix SATA port maps
Previously incorrect sets of SATA ports were enabled.
There are no publically available schematics, but I am almost certain
the new values are correct.
The original 0x33 value was carlessly copy pasted, and only enables
ports 0, 1, 4, 5, leaving 2, 3 disabled.
On the SFF, with 0x33 only the first 2 ports worked. I have verified
by plugging in devices under the stock firmware that 0, 1, 2 are the
ones that should be enabled, so setting the value to 0x7 per datasheet.
This was also tested in practice to work.
I don't have an MT, but I was told the two white ports didn't work
with 0x33, so those are most certainly ports 3, 4, hence me setting
the value to 0xf. If the MT's working ports are port 0, 1 on the PCH
this is correct.
Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
Change-Id: I32cb236b8f8140fba4a04c23161363d21741dcbc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81550
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Diffstat (limited to 'src/mainboard/dell/optiplex_9020/overridetree_mt.cb')
| -rw-r--r-- | src/mainboard/dell/optiplex_9020/overridetree_mt.cb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/dell/optiplex_9020/overridetree_mt.cb b/src/mainboard/dell/optiplex_9020/overridetree_mt.cb index 90205c2d68..a7819601b9 100644 --- a/src/mainboard/dell/optiplex_9020/overridetree_mt.cb +++ b/src/mainboard/dell/optiplex_9020/overridetree_mt.cb @@ -3,6 +3,8 @@ chip northbridge/intel/haswell device domain 0 on chip southbridge/intel/lynxpoint + register "sata_port_map" = "0xf" + device pci 1c.1 on end # PCI (via XIO2001 bridge) device pci 1c.2 on end # PCIe 1x slot end |