diff options
author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2020-04-13 21:42:24 +0200 |
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committer | Michał Żygowski <michal.zygowski@3mdeb.com> | 2020-05-16 17:38:46 +0000 |
commit | 72f06ca554e6f7b155a6b4e2b8ce57942288ac2c (patch) | |
tree | bb4341a075b603d0d7e3778a7b10978cbf494c1d /src/mainboard/dell/optiplex_9010/romstage.c | |
parent | fba08308f086d7b77f95554df094288fd55903d1 (diff) |
mb/dell/optiplex_9010: Add Dell OptiPlex 9010 SFF support
Based on the autoport. The OptiPlex 9010 comes in four different sizes:
MT, DT, SFF and USFF. Tested on SFF only. The other PCBs are slightly
different, but they are designed with intercompatibility in mind. With
small devicetree overrides it should work on OptiPlex 7010 and other
OptiPlex 9010 variants as well.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I88d65cae30d08ca727d86d930707c2be25a527cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40351
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/dell/optiplex_9010/romstage.c')
-rw-r--r-- | src/mainboard/dell/optiplex_9010/romstage.c | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/src/mainboard/dell/optiplex_9010/romstage.c b/src/mainboard/dell/optiplex_9010/romstage.c new file mode 100644 index 0000000000..36af6e49c0 --- /dev/null +++ b/src/mainboard/dell/optiplex_9010/romstage.c @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <arch/io.h> +#include <console/console.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <superio/smsc/sch5545/sch5545.h> +#include <superio/smsc/sch5545/sch5545_emi.h> + +#include "sch5545_ec.h" + +void mainboard_early_init(int s3resume) +{ + uint16_t ec_fw_version; + + /* + * We do EC initialization in romstage, because it makes no sense to + * bloat the bootblock any more. Secondly, the EC expects to receive + * correct initialization sequence from the host in the time window of + * about 3-5 seconds since system reset. If it doesn't receive the + * initialization sequence, it enters an error path which results in + * fans spinned up to high speed. In this state EC doesn't respond to + * further messages sent over EMI. The issue appears after power + * failure, where EC loses its configuration. For this particular + * reasons we do the initialization in romstage instead of ramstage. + */ + sch5545_emi_init(0x2e); + if (sch5545_emi_get_int_mask_high()) + printk(BIOS_SPEW, "EC interrupt mask MSB is not 0\n"); + + sch5545_ec_hwm_early_init(); + + if (!s3resume) { + ec_fw_version = sch5545_get_ec_fw_version(); + printk(BIOS_DEBUG, "SCH5545 EC firmware version %04x\n", ec_fw_version); + sch5545_update_ec_firmware(ec_fw_version); + } + printk(BIOS_DEBUG, "EC early init complete.\n"); + + /* Disable SMIs and clear SMI status */ + outb(0, SCH5545_RUNTIME_REG_BASE + SCH5545_RR_SMI_EN); + outb(SCH5545_SMI_GLOBAL_STS, SCH5545_RUNTIME_REG_BASE + SCH5545_RR_SMI_STS); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} |