diff options
| author | Bora Guvendik <bora.guvendik@intel.com> | 2024-08-06 14:00:23 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-08-09 17:59:44 +0000 |
| commit | d4253a3d563db46268db0a2fafb5314c0dd3c312 (patch) | |
| tree | 9fe73d48c0d28143b8bdde04f4339f38c010c851 /src/mainboard/clevo | |
| parent | b0be97b68bea00b1fc8f8e6089543fb429235951 (diff) | |
device/pci_ids: Add new Intel PTL device IDs for Tracehub
This patch adds new North Peak PCI device IDs for Intel PTL-U and PTL-H.
Additionally, updates the tracehub driver's `pci_device_ids` list to
include these new IDs.
Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2
BUG=b:347669091
TEST=Boot to OS using PTL Silicon, verify if above 4GB IMR region is
reserved.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Ifa1a0a57c504e06d686e7e0826547251b456cc8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83786
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/clevo')
0 files changed, 0 insertions, 0 deletions