diff options
| author | Furquan Shaikh <furquan@google.com> | 2020-10-04 12:52:54 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-10-13 17:38:38 +0000 |
| commit | a266d1e63a3e695e85e922a853da928f1807e534 (patch) | |
| tree | dbca706ff5f2e0d39014b928e1bba1a196a44db5 /src/mainboard/clevo | |
| parent | a1ddd2a15d3238befdf257c33e569e6e5773f93f (diff) | |
mb, soc/intel: Switch to using drivers/wifi/generic for Intel WiFi devices
This change switches all mainboard devices to use drivers/wifi/generic
instead of drivers/intel/wifi chip driver for Intel WiFi
devices. There is no need for two separate chip drivers in coreboot to
handle Intel and non-Intel WiFi devices since the differences can be
handled at runtime using the PCI vendor ID. This also allows mainboard
to easily multi-source WiFi chips and still use the same firmware
image without having to distinguish between the chip drivers.
BUG=b:169802515
BRANCH=zork
Change-Id: Ieac603a970cb2c9bf835021d1fb0fd07fd535280
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'src/mainboard/clevo')
| -rw-r--r-- | src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index 3ee20e9c4b..8f256ad7fb 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -89,7 +89,7 @@ chip soc/intel/cannonlake register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 3 end device pci 14.1 off end # USB xDCI (OTG) - chip drivers/intel/wifi # CNVi wifi + chip drivers/wifi/generic # CNVi wifi register "wake" = "GPE0_PME_B0" device pci 14.3 on end end @@ -141,7 +141,7 @@ chip soc/intel/cannonlake end device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 on # PCI Express Port 8 - chip drivers/intel/wifi + chip drivers/wifi/generic device pci 00.0 on end # x1 M.2/E 2230 (J_WLAN1) end register "PcieRpEnable[7]" = "1" |