soc/intel/meteorlake: Configure DDR5 Physical channel width to 64

A DDR5 DIMM internally has two channels each of width 32 bit.
But the total physical channel width is 64 bit.

This is the same fix as be5dc3daa "soc/intel/alderlake: Configure DDR5
Physical channel width to 64"

Building with GCC LTO cought this buffer overflow when assigning SPD
addresses to a buffer.

Change-Id: Ief6018e4dcce6b26804ff864cdfe116f0f90d545
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>

0 files changed, 0 insertions, 0 deletions