diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2021-11-22 21:13:49 +0100 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2022-11-11 22:43:01 +0000 |
| commit | d6ac7a9a3a774eb5a70385660c072bbaa248a355 (patch) | |
| tree | 291e111800b27c7f27cd79044a62a07e5f1cc799 /src/mainboard/clevo/cml-u/variants | |
| parent | e1e65cb0f1cad6117d48503f2f78d115caecc55b (diff) | |
mb/clevo/l140cu: drop System76 EC
Drop System76 EC, since the ODM board does not use it. Clevo EC FW
support will be added and hooked up cleanly in the follow-up changes.
Change-Id: I06abbde238be6d25842472a6a82159413ab52ef5
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59816
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/clevo/cml-u/variants')
| -rw-r--r-- | src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index bfcc046157..7385fe19c6 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -183,13 +183,6 @@ chip soc/intel/cannonlake device pci 1e.2 off end # GSPI #0 device pci 1e.3 off end # GSPI #1 device pci 1f.0 on # LPC Interface - # LPC configuration from lspci -s 1f.0 -xxx - # Address 0x88: Decode 0x68 - 0x6F (EC PM channel) - register "gen1_dec" = "0x00040069" - # Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command) - register "gen2_dec" = "0x00fc0e01" - # Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug) - register "gen3_dec" = "0x00fc0f01" chip drivers/pc80/tpm # TPM device pnp 0c31.0 on end end |