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| author | Bernardo Perez Priego <bernardo.perez.priego@intel.com> | 2021-05-18 18:39:19 -0700 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-06-18 21:42:35 +0000 |
| commit | 095f97b58f10087b1350e62d8162827c8689c7a2 (patch) | |
| tree | 30f980d1280790b74d31e571a534d96929857d1e /src/mainboard/clevo/cml-u/variants/l140cu/data.vbt | |
| parent | 193ee64d52a707809982231cd857329fe17f9f99 (diff) | |
soc/intel/alderlake: Add TBT PCIe root ports enablement
Ports are enabled according to devicetree.
BUG=none
TEST=Boot device, TBT should be functional
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I57e8eb13484014c17d24ad564643f0d03d11bc58
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/clevo/cml-u/variants/l140cu/data.vbt')
0 files changed, 0 insertions, 0 deletions