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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-01-23 00:18:08 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-01-24 18:16:17 +0000 |
| commit | cc975c5c65c27f13c00dc7eabec02386002a2c53 (patch) | |
| tree | 76d675734dce3a4b34fb86285873fa6258e0c39e /src/mainboard/cavium | |
| parent | f09221c033a27d87f39ab074ee53a109a861f096 (diff) | |
soc/amd/cezanne/Kconfig: select missing SSE2 option
This will set the corresponding enable bit in CR4 in bootblock_crt0.S
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I648a83fbcb71456bf1e5b11c491e7cadc8e0e281
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/mainboard/cavium')
0 files changed, 0 insertions, 0 deletions