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authorLin Huang <hl@rock-chips.com>2016-03-23 19:24:53 +0800
committerPatrick Georgi <pgeorgi@google.com>2016-05-09 08:46:42 +0200
commitbf48fbbcc116b79fa5bfe05db83c354ee87e3843 (patch)
treeec259ca22f496383fad4ab8a18a265c09c64b838 /src/mainboard/azza
parent08d177b091be4758c7b541a5f9550b849e6dd092 (diff)
rockchip: rk3399: support saradc
This patch add functions to configure saradc clk and get saradc's raw value for each channel. Currently add saradc to ramstage. Please refer to TRM V0.3 Part 2 Chapter 18 for this IP. BRANCH=none BUG=chrome-os-partner:51537 TEST=on kevin board, get the raw value 61 for channel 0, measure the ADC_IN0 as 0.109V, 61.0/1024 = 0.05957 0.109V/1.8V = 0.06056 Change-Id: Ic198b2a964ccf8bb687441f0e2702665402fff6e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bc400316de2d75eccad3990a4187bf2dc49a844a Original-Change-Id: I542430ed97bd27f9bfcec89b1d703d9fa390d4e0 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/334177 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14720 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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