Drop GX1, CS5330 and related boards

There is no Cache As Ram for these boards, let's get rid of them.

Change-Id: Ib41f8cd64fc9a440838aea86076d6514aacb301c
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/7117
Reviewed-by: Marc Jones <marc.jones@se-eng.com>

5 files changed, 0 insertions, 266 deletions

diff --git a/src/mainboard/axus/tc320/Kconfig b/src/mainboard/axus/tc320/Kconfig
deleted file mode 100644
index 97c33aaebb..0000000000
--- a/src/mainboard/axus/tc320/Kconfig
+++ /dev/null
@@ -1,46 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-##
-if BOARD_AXUS_TC320
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-	select CPU_AMD_GEODE_GX1
-	select NORTHBRIDGE_AMD_GX1
-	select SOUTHBRIDGE_AMD_CS5530
-	select SUPERIO_NSC_PC97317
-	select ROMCC
-	select HAVE_PIRQ_TABLE
-	select PIRQ_ROUTE
-	select UDELAY_TSC
-	select BOARD_ROMSIZE_KB_256
-
-config MAINBOARD_DIR
-	string
-	default axus/tc320
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "TC320"
-
-# Soldered NIC, internal USB, no real PCI slots.
-config IRQ_SLOT_COUNT
-	int
-	default 2
-
-endif # BOARD_AXUS_TC320
diff --git a/src/mainboard/axus/tc320/board_info.txt b/src/mainboard/axus/tc320/board_info.txt
deleted file mode 100644
index 005c28d14c..0000000000
--- a/src/mainboard/axus/tc320/board_info.txt
+++ /dev/null
@@ -1,2 +0,0 @@
-Category: settop
-Board URL: http://www.keyton.co.jp/products/UAXT/TC-320.html
diff --git a/src/mainboard/axus/tc320/devicetree.cb b/src/mainboard/axus/tc320/devicetree.cb
deleted file mode 100644
index 970f71fb13..0000000000
--- a/src/mainboard/axus/tc320/devicetree.cb
+++ /dev/null
@@ -1,55 +0,0 @@
-chip northbridge/amd/gx1		# Northbridge
-  device domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    chip southbridge/amd/cs5530		# Southbridge
-      device pci 12.0 on		# ISA bridge
-        chip superio/nsc/pc97317	# Super I/O
-          device pnp 2e.0 on		# PS/2 keyboard
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1
-          end
-          device pnp 2e.1 on		# PS/2 mouse
-            irq 0x70 = 12
-          end
-          device pnp 2e.2 on		# RTC, advanced power control (APC)
-            io 0x60 = 0x70
-            irq 0x70 = 8
-          end
-          device pnp 2e.3 off		# Floppy (N/A on this board)
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 2e.4 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-          end
-          device pnp 2e.5 off		# COM2
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 2e.6 on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 2e.7 on		# GPIO
-            io 0x60 = 0xe0
-          end
-          device pnp 2e.8 on		# Power management
-            io 0x60 = 0xe800
-          end
-        end
-      end
-      device pci 12.1 off end		# SMI
-      device pci 12.2 off end		# IDE
-      device pci 12.3 on end		# Audio
-      device pci 12.4 on end		# VGA (onboard)
-      device pci 13.0 on end		# USB
-      # register "ide0_enable" = "1"
-      # register "ide1_enable" = "1"
-    end
-  end
-  chip cpu/amd/geode_gx1		# CPU
-  end
-end
diff --git a/src/mainboard/axus/tc320/irq_tables.c b/src/mainboard/axus/tc320/irq_tables.c
deleted file mode 100644
index 71cf2e1ef7..0000000000
--- a/src/mainboard/axus/tc320/irq_tables.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Juergen Beisert <juergen@kreuzholzen.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/**
- * @file
- * Interrupt routing description for the AXUS TC320 board.
- * It was not possible to read back the PIRQ table. There was no BIOS to ask
- * for it, only a bootloader for an embedded OS.
- * But with the method described here:
- *    http://coreboot.org/Creating_Valid_IRQ_Tables
- * it was possible to detect the physical IRQ routing on this board.
- *
- * This is the physical routing on this board:
- *
- *    IRQ          5530       USB     Network
- * controller  northbridge  device     device
- *                          00.13.0   00.0e.00
- * --------------------------------------------
- *    11          INTA#      INTA#      n.c.
- *    15          INTB#       n.c.     INTA#
- *                INTC#       n.c.      n.c.
- *                INTD#       n.c.      n.c.
- */
-
-#include <arch/pirq_routing.h>
-
-#define INT_A 0x01
-#define INT_B 0x02
-#define INT_C 0x03
-#define INT_D 0x04
-
-/*
- * The USB controller should be connected to IRQ11,
- * the network controller should be connected to IRQ15.
- */
-
-#define IRQ_BITMAP_LINK0 0x0800
-#define IRQ_BITMAP_LINK1 0x8000
-#define IRQ_BITMAP_LINK2 0x0000
-#define IRQ_BITMAP_LINK3 0x0000
-
-/** Reserved interrupt channels for exclusive PCI usage. */
-#define IRQ_DEVOTED_TO_PCI (IRQ_BITMAP_LINK0 | IRQ_BITMAP_LINK1)
-
-/**
- * Routing description.
- * Documentation at: http://www.microsoft.com/whdc/archive/pciirq.mspx
- */
-static const struct irq_routing_table intel_irq_routing_table = {
-	.signature = PIRQ_SIGNATURE,	/* PIRQ signature */
-	.version = PIRQ_VERSION,	/* PIRQ version */
-	.size = 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. CONFIG_IRQ_SLOT_COUNT devices */
-	.rtr_bus = 0x00,		/* Interrupt router bus */
-	.rtr_devfn = (0x12 << 3) | 0x0,	/* Interrupt router device */
-	.exclusive_irqs = IRQ_DEVOTED_TO_PCI,	/* IRQs devoted to PCI */
-	.rtr_vendor = 0x1078,		/* Vendor */
-	.rtr_device = 0x0100,		/* Device */
-	.miniport_data = 0,		/* Miniport data */
-	.checksum = 0xe3,		/* Checksum */
-	.slots = {
-		/*
-		 * Definition for "slot#1". There is no real slot,
-		 * the USB device is embedded...
-		 */
-		[0] = {
-			.bus = 0x00,
-			.devfn = (0x13 << 3) | 0x0,
-			.irq = {
-				/*      Link   Bitmap */
-				[0] = { INT_A, IRQ_BITMAP_LINK0 },
-				[1] = { INT_B, IRQ_BITMAP_LINK1 },
-				[2] = { INT_C, IRQ_BITMAP_LINK2 },
-				[3] = { INT_D, IRQ_BITMAP_LINK3 },
-			},
-			.slot = 0x0,
-		},
-		/*
-		 * Definition for "slot#2". There is no real slot,
-		 * the network device is soldered...
-		 */
-		[1] = {
-			.bus = 0x00,
-			.devfn = (0x0e << 3) | 0x0,
-			.irq = {
-				/*      Link   Bitmap */
-				[0] = { INT_B, IRQ_BITMAP_LINK1 },
-				[1] = { INT_C, IRQ_BITMAP_LINK2 },
-				[2] = { INT_D, IRQ_BITMAP_LINK3 },
-				[3] = { INT_A, IRQ_BITMAP_LINK0	},
-			},
-			.slot = 0x0,
-		}
-	}
-};
-
-/**
- * Copy the IRQ routing table to memory.
- *
- * @param[in] addr Destination address (between 0xF0000...0x100000).
- * @return TODO.
- */
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/axus/tc320/romstage.c b/src/mainboard/axus/tc320/romstage.c
deleted file mode 100644
index 158a45fbde..0000000000
--- a/src/mainboard/axus/tc320/romstage.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Juergen Beisert <juergen@kreuzholzen.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <console/console.h>
-#include "northbridge/amd/gx1/raminit.c"
-#include "superio/nsc/pc97317/early_serial.c"
-#include "cpu/x86/bist.h"
-#include "southbridge/amd/cs5530/enable_rom.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1)
-
-#include <cpu/intel/romstage.h>
-static void main(unsigned long bist)
-{
-	pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-	console_init();
-	report_bist_failure(bist);
-	cs5530_enable_rom();
-	sdram_init();
-}