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authorKeith Hui <buurin@gmail.com>2024-02-05 19:18:43 -0500
committerMartin L Roth <gaumless@gmail.com>2024-06-08 00:19:23 +0000
commita911b758482025d46e132eeb2ed0279b65692075 (patch)
treefb8475ef03a0365132fefb82bc248468ef0a4784 /src/mainboard/asus/p8x7x-series
parentee126348726b24fbf6e5435bb2cf15417959a8f7 (diff)
mb/*: Remove old USB configurations from SNB/bd82x6x boards
Remove USB configurations and data structures from northbridge devicetree (SNB+MRC boards) and bootblock/romstage C code (native-only SNB boards). All USB configurations are drawn from southbridge devicetree going forward. Change-Id: Ie1cd21077136998a6e90050c95263f2efed68a67 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81882 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/asus/p8x7x-series')
-rw-r--r--src/mainboard/asus/p8x7x-series/devicetree.cb5
-rw-r--r--src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c17
-rw-r--r--src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c17
-rw-r--r--src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c18
-rw-r--r--src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb5
-rw-r--r--src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c18
-rw-r--r--src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb5
-rw-r--r--src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c17
-rw-r--r--src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c17
9 files changed, 0 insertions, 119 deletions
diff --git a/src/mainboard/asus/p8x7x-series/devicetree.cb b/src/mainboard/asus/p8x7x-series/devicetree.cb
index 4052cf43ad..e9b97bc7ba 100644
--- a/src/mainboard/asus/p8x7x-series/devicetree.cb
+++ b/src/mainboard/asus/p8x7x-series/devicetree.cb
@@ -7,11 +7,6 @@ chip northbridge/intel/sandybridge
register "max_mem_clock_mhz" = "800"
register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}"
- register "usb_port_config" = "{
- {1, 0, 0x0080}, {1, 0, 0x0080}, {1, 1, 0x0080}, {1, 1, 0x0080}, {1, 2, 0x0080},
- {1, 2, 0x0080}, {1, 3, 0x0080}, {1, 3, 0x0080}, {1, 4, 0x0080}, {1, 4, 0x0080},
- {1, 6, 0x0080}, {1, 5, 0x0080}, {1, 5, 0x0080}, {1, 6, 0x0080}
- }"
# 4 bit switch mask. 0=not switchable, 1=switchable
# Means once it's loaded the OS, it can swap ports
# from/to EHCI/xHCI. Z77 has four USB3 ports, so 0xf
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c
index 79b67f07f1..1e21f2062b 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c
+++ b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c
@@ -10,23 +10,6 @@
#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1)
#define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI)
-const struct southbridge_usb_port mainboard_usb_ports[] = {
- { 1, 0, 0 },
- { 1, 0, 0 },
- { 1, 0, 1 },
- { 1, 0, 1 },
- { 1, 0, 2 },
- { 1, 0, 2 },
- { 1, 0, 3 },
- { 1, 0, 3 },
- { 1, 0, 4 },
- { 1, 0, 4 },
- { 1, 0, 6 },
- { 1, 0, 5 },
- { 1, 0, 5 },
- { 1, 0, 6 },
-};
-
void bootblock_mainboard_early_init(void)
{
nuvoton_pnp_enter_conf_state(GLOBAL_DEV);
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c
index 89f9eee106..056dfd467d 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c
+++ b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c
@@ -10,23 +10,6 @@
#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1)
#define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI)
-const struct southbridge_usb_port mainboard_usb_ports[] = {
- { 1, 0, 0 },
- { 1, 0, 0 },
- { 1, 0, 1 },
- { 1, 0, 1 },
- { 1, 0, 2 },
- { 1, 0, 2 },
- { 1, 0, 3 },
- { 1, 0, 3 },
- { 1, 0, 4 },
- { 1, 0, 4 },
- { 1, 0, 6 },
- { 1, 0, 5 },
- { 1, 0, 5 },
- { 1, 0, 6 },
-};
-
void bootblock_mainboard_early_init(void)
{
nuvoton_pnp_enter_conf_state(GLOBAL_DEV);
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c
index 4656617290..6897658ad5 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c
@@ -12,24 +12,6 @@
#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1)
-const struct southbridge_usb_port mainboard_usb_ports[] = {
- /* {enable, current, oc_pin} */
- {1, 8, 0}, /* Port 0: USB3 front internal header, top */
- {1, 8, 0}, /* Port 1: USB3 front internal header, bottom */
- {1, 2, 1}, /* Port 2: USB3 rear, top */
- {1, 2, 1}, /* Port 3: USB3 rear, bottom */
- {1, 2, 2}, /* Port 4: USB2 rear, PS2 top */
- {1, 2, 2}, /* Port 5: USB2 rear, PS2 bottom */
- {1, 2, 3}, /* Port 6: USB2 rear, ETH, top */
- {1, 2, 3}, /* Port 7: USB2 rear, ETH, bottom */
- {1, 9, 4}, /* Port 8: USB2 internal header USB910, top */
- {1, 9, 4}, /* Port 9: USB2 internal header USB910, bottom */
- {1, 2, 6}, /* Port 10: USB2 internal header USB1112, top */
- {1, 2, 5}, /* Port 11: USB2 internal header USB1112, bottom */
- {1, 2, 5}, /* Port 12: USB2 internal header USB1314, top */
- {1, 2, 6} /* Port 13: USB2 internal header USB1314, bottom */
-};
-
void bootblock_mainboard_early_init(void)
{
nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
index 45ad0e19f1..6232c9be83 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
@@ -1,11 +1,6 @@
## SPDX-License-Identifier: GPL-2.0-only
chip northbridge/intel/sandybridge
- register "usb_port_config" = "{
- {1, 0, 0x0040}, {1, 0, 0x0040}, {1, 1, 0x0130}, {1, 1, 0x0130}, {1, 2, 0x0130},
- {1, 2, 0x0130}, {1, 3, 0x0130}, {1, 3, 0x0130}, {1, 4, 0x0080}, {1, 4, 0x0080},
- {1, 6, 0x0130}, {1, 5, 0x0130}, {1, 5, 0x0130}, {1, 6, 0x0130}
- }"
device domain 0 on
subsystemid 0x1043 0x84ca inherit
chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c
index cec5070a10..4940b54eb9 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c
@@ -14,24 +14,6 @@
#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP2)
-const struct southbridge_usb_port mainboard_usb_ports[] = {
- /* {enable, current, oc_pin} */
- { 1, 2, 0 }, /* Port 0: USB3 front internal header, top */
- { 1, 2, 0 }, /* Port 1: USB3 front internal header, bottom */
- { 1, 2, 1 }, /* Port 2: USB3 rear, ETH top */
- { 1, 2, 1 }, /* Port 3: USB3 rear, ETH bottom */
- { 1, 2, 2 }, /* Port 4: USB2 rear, PS2 top */
- { 1, 2, 2 }, /* Port 5: USB2 rear, PS2 bottom */
- { 1, 2, 3 }, /* Port 6: USB2 internal header USB78, top */
- { 1, 2, 3 }, /* Port 7: USB2 internal header USB78, bottom */
- { 1, 2, 4 }, /* Port 8: USB2 internal header USB910, top */
- { 1, 2, 4 }, /* Port 9: USB2 internal header USB910, bottom */
- { 1, 2, 6 }, /* Port 10: USB2 internal header USB1112, top */
- { 1, 2, 5 }, /* Port 11: USB2 internal header USB1112, bottom */
- { 0, 2, 5 }, /* Port 12: Unused. Asus proprietary DEBUG_PORT ??? */
- { 0, 2, 6 } /* Port 13: Unused. Asus proprietary DEBUG_PORT ??? */
-};
-
void bootblock_mainboard_early_init(void)
{
nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb
index 2cb94213e3..4613c128e2 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb
@@ -1,11 +1,6 @@
## SPDX-License-Identifier: GPL-2.0-only
chip northbridge/intel/sandybridge
- register "usb_port_config" = "{
- {1, 0, 0x0080}, {1, 0, 0x0080}, {1, 1, 0x0080}, {1, 1, 0x0080}, {1, 2, 0x0080},
- {1, 2, 0x0080}, {1, 3, 0x0080}, {1, 3, 0x0080}, {1, 4, 0x0080}, {1, 4, 0x0080},
- {1, 6, 0x0080}, {1, 5, 0x0080}, {0, 5, 0x0080}, {0, 6, 0x0080}
- }"
device domain 0 on
subsystemid 0x1043 0x84ca inherit
chip southbridge/intel/bd82x6x
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c
index c16b055aa4..290523f5fd 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c
@@ -11,23 +11,6 @@
#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1)
#define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI)
-const struct southbridge_usb_port mainboard_usb_ports[] = {
- { 1, 2, 0 },
- { 1, 2, 0 },
- { 1, 2, 1 },
- { 1, 0, 1 },
- { 1, 0, 2 },
- { 1, 2, 2 },
- { 1, 2, 3 },
- { 1, 2, 3 },
- { 1, 2, 4 },
- { 1, 0, 4 },
- { 1, 2, 6 },
- { 1, 2, 5 },
- { 1, 2, 5 },
- { 1, 2, 6 },
-};
-
void bootblock_mainboard_early_init(void)
{
nuvoton_pnp_enter_conf_state(GLOBAL_DEV);
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c
index 89f9eee106..056dfd467d 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c
@@ -10,23 +10,6 @@
#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1)
#define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI)
-const struct southbridge_usb_port mainboard_usb_ports[] = {
- { 1, 0, 0 },
- { 1, 0, 0 },
- { 1, 0, 1 },
- { 1, 0, 1 },
- { 1, 0, 2 },
- { 1, 0, 2 },
- { 1, 0, 3 },
- { 1, 0, 3 },
- { 1, 0, 4 },
- { 1, 0, 4 },
- { 1, 0, 6 },
- { 1, 0, 5 },
- { 1, 0, 5 },
- { 1, 0, 6 },
-};
-
void bootblock_mainboard_early_init(void)
{
nuvoton_pnp_enter_conf_state(GLOBAL_DEV);
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-15 15:50:04 +0000