diff options
| author | Keith Hui <buurin@gmail.com> | 2024-05-31 23:19:40 -0400 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2024-06-08 00:10:10 +0000 |
| commit | 0aa069fb10d179a31159d323800eb363e7769661 (patch) | |
| tree | bf124411c591e34a405ea65c23644f183b2a8c59 /src/mainboard/asus/p8x7x-series/variants/p8z77-m | |
| parent | 51a57eb5ea782c3287719c8c7646ea726b14c78d (diff) | |
mb/asus/p8z77-m: Update USB current map to match vendor
This board has used the USB current map from asus/p8z77-m_pro since it
first landed in coreboot, which actually doesn't match vendor firmware.
Apply values obtained from hardware while running vendor firmware
to both native and MRC config.
Change-Id: I7ce13493c3ecac8154460c1fedf05e2d70a8e394
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82756
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/asus/p8x7x-series/variants/p8z77-m')
| -rw-r--r-- | src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c | 8 | ||||
| -rw-r--r-- | src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb | 22 |
2 files changed, 23 insertions, 7 deletions
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c index 47c5cb302d..4656617290 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c @@ -14,16 +14,16 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { /* {enable, current, oc_pin} */ - {1, 2, 0}, /* Port 0: USB3 front internal header, top */ - {1, 2, 0}, /* Port 1: USB3 front internal header, bottom */ + {1, 8, 0}, /* Port 0: USB3 front internal header, top */ + {1, 8, 0}, /* Port 1: USB3 front internal header, bottom */ {1, 2, 1}, /* Port 2: USB3 rear, top */ {1, 2, 1}, /* Port 3: USB3 rear, bottom */ {1, 2, 2}, /* Port 4: USB2 rear, PS2 top */ {1, 2, 2}, /* Port 5: USB2 rear, PS2 bottom */ {1, 2, 3}, /* Port 6: USB2 rear, ETH, top */ {1, 2, 3}, /* Port 7: USB2 rear, ETH, bottom */ - {1, 2, 4}, /* Port 8: USB2 internal header USB910, top */ - {1, 2, 4}, /* Port 9: USB2 internal header USB910, bottom */ + {1, 9, 4}, /* Port 8: USB2 internal header USB910, top */ + {1, 9, 4}, /* Port 9: USB2 internal header USB910, bottom */ {1, 2, 6}, /* Port 10: USB2 internal header USB1112, top */ {1, 2, 5}, /* Port 11: USB2 internal header USB1112, bottom */ {1, 2, 5}, /* Port 12: USB2 internal header USB1314, top */ diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb index b3d05fe3ec..45ad0e19f1 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb @@ -2,14 +2,30 @@ chip northbridge/intel/sandybridge register "usb_port_config" = "{ - {1, 0, 0x0080}, {1, 0, 0x0080}, {1, 1, 0x0080}, {1, 1, 0x0080}, {1, 2, 0x0080}, - {1, 2, 0x0080}, {1, 3, 0x0080}, {1, 3, 0x0080}, {1, 4, 0x0080}, {1, 4, 0x0080}, - {1, 6, 0x0080}, {1, 5, 0x0080}, {1, 5, 0x0080}, {1, 6, 0x0080} + {1, 0, 0x0040}, {1, 0, 0x0040}, {1, 1, 0x0130}, {1, 1, 0x0130}, {1, 2, 0x0130}, + {1, 2, 0x0130}, {1, 3, 0x0130}, {1, 3, 0x0130}, {1, 4, 0x0080}, {1, 4, 0x0080}, + {1, 6, 0x0130}, {1, 5, 0x0130}, {1, 5, 0x0130}, {1, 6, 0x0130} }" device domain 0 on subsystemid 0x1043 0x84ca inherit chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH register "gen1_dec" = "0x000c0291" + register "usb_port_config" = "{ + {1, 8, 0}, /* Port 0: USB3 front internal header, top */ + {1, 8, 0}, /* Port 1: USB3 front internal header, bottom */ + {1, 2, 1}, /* Port 2: USB3 rear, top */ + {1, 2, 1}, /* Port 3: USB3 rear, bottom */ + {1, 2, 2}, /* Port 4: USB2 rear PS2, top */ + {1, 2, 2}, /* Port 5: USB2 rear PS2, bottom */ + {1, 2, 3}, /* Port 6: USB2 rear LAN, top */ + {1, 2, 3}, /* Port 7: USB2 rear LAN, bottom */ + {1, 9, 4}, /* Port 8: USB2 internal header USB910, top */ + {1, 9, 4}, /* Port 9: USB2 internal header USB910, bottom */ + {1, 2, 6}, /* Port 10: USB2 internal header USB1112, top */ + {1, 2, 5}, /* Port 11: USB2 internal header USB1112, bottom */ + {1, 2, 5}, /* Port 12: USB2 internal header USB1314, top */ + {1, 2, 6} /* Port 13: USB2 internal header USB1314, bottom */ + }" device ref pcie_rp1 on end # PCIe x4 slot device ref pcie_rp2 off end |