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author | Jamie Ryu <jamie.m.ryu@intel.com> | 2020-08-18 19:10:43 -0700 |
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committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-09-30 15:27:18 +0000 |
commit | 80535953707ba925aefc7c40318d6318178f04cf (patch) | |
tree | 14059f1d143983c6a2daeebda16f41c84aa2fc5c /src/mainboard/asus/p8h61-m_lx/early_init.c | |
parent | 075df92298fe3bb0ef04233395effe668c4a5550 (diff) |
mb/google/volteer: Update SLP_Sx assertion widths and PwrCycDur
This patch updates the SLP_Sx assertion widths and power cycle duration
for volteer.
Power cycle duration:
With default value,
S0->S5 -> [ ~4.2 seconds delay ] -> S5->S0
With value set to 1,
S0->S5 -> [ ~1.2 seconds delay ] -> S5->S0
BUG=b:159108661
TEST=Verified that the power cycle duration is 1~2s with a global reset
on volteer.
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: Idf4e0c3a60b4ac59e31df1357f2ff28f195ff17f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Diffstat (limited to 'src/mainboard/asus/p8h61-m_lx/early_init.c')
0 files changed, 0 insertions, 0 deletions