diff options
author | Arthur Heymans <arthur@aheymans.xyz> | 2019-02-05 13:30:11 +0100 |
---|---|---|
committer | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-09 05:37:09 +0000 |
commit | 7e4bfe4b91cc8dbc18a4b940c26f372e471d49db (patch) | |
tree | 8aa6245999e024b4c8871bf4819655a549329d2e /src/mainboard/asus/p5ql-em/dsdt.asl | |
parent | b8df689a6aaaa721103ed75d647decad2b4a9528 (diff) |
mb/asus/p5ql-em: Add mainboard
Tested, working:
- First dimm slot of each channel
- USB, SATA
- CPU FSB at 800, 1067 and 1333MHz
- Libgfxinit on DVI and VGA slot
- PCI slot
- Realtek NIC (configure MAC address in Kconfig)
- PEG slot
- PS2 keyboard
Tested, not working:
- second dimm slot for each channel. Those are hooked up to the second
rank of the channel, instead of rank 3 and 4. The raminit does not
support such setups.
Untested:
- PCIe x1 slot, likely works fine
- HDMI
Tested using SeaBIOS 1.12, Linux 4.19.
Change-Id: I88fe9c66dae079cd7eedcc9736c5922defbc0e5a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/asus/p5ql-em/dsdt.asl')
-rw-r--r-- | src/mainboard/asus/p5ql-em/dsdt.asl | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/src/mainboard/asus/p5ql-em/dsdt.asl b/src/mainboard/asus/p5ql-em/dsdt.asl new file mode 100644 index 0000000000..632c6cba2a --- /dev/null +++ b/src/mainboard/asus/p5ql-em/dsdt.asl @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/i82801jx/i82801jx.h> + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x00000001 // OEM revision +) +{ + // global NVS and variables + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/i82801jx/acpi/globalnvs.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/x4x/acpi/x4x.asl> + #include <southbridge/intel/i82801jx/acpi/ich10.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/common/acpi/sleepstates.asl> +} |