mainboard/asus/p3b-f: Reintroduce as variant of p2b

Fold this last ASUS 440BX board into the P2B family, while bringing in
some changes:

- Devicetree becomes overridetree.
- Remove non-existent IR device and disable ACPI device on Super I/O to
  match OEM firmware.
- Add SB GPO settings from OEM firmware to devicetree. This disables
  the SPD enabling magic this board needs. By moving the enabling part
  to bootblock the hacky enable_spd hook can be eliminated.
- Initialize the serial port in bootblock, like the other boards.

Boot tested on hardware.

Change-Id: I65f2cb9d1bd4c82550de43889e3502526a46bd18
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41047
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

4 files changed, 90 insertions, 0 deletions

diff --git a/src/mainboard/asus/p2b/variants/p3b-f/board_info.txt b/src/mainboard/asus/p2b/variants/p3b-f/board_info.txt
new file mode 100644
index 0000000000..a1657431b7
--- /dev/null
+++ b/src/mainboard/asus/p2b/variants/p3b-f/board_info.txt
@@ -0,0 +1,7 @@
+Category: desktop
+Board URL: ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p3b-f/
+ROM package: DIP32
+ROM protocol: Parallel
+ROM socketed: y
+Flashrom support: y
+Release year: 1999
diff --git a/src/mainboard/asus/p2b/variants/p3b-f/irq_tables.c b/src/mainboard/asus/p2b/variants/p3b-f/irq_tables.c
new file mode 100644
index 0000000000..c0c5aa25da
--- /dev/null
+++ b/src/mainboard/asus/p2b/variants/p3b-f/irq_tables.c
@@ -0,0 +1,34 @@
+/* This file is part of the coreboot project. */
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <arch/pirq_routing.h>
+
+static const struct irq_routing_table intel_irq_routing_table = {
+	PIRQ_SIGNATURE,
+	PIRQ_VERSION,
+	32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
+	0x00,			/* Interrupt router bus */
+	(0x04 << 3) | 0x0,	/* Interrupt router device */
+	0,			/* IRQs devoted exclusively to PCI usage */
+	0x8086,			/* Vendor */
+	0x122e,			/* Device */
+	0,			/* Miniport data */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+	0x95,			/* Checksum */
+	{
+		/* bus,       dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
+		{0x00,(0x0c << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0},
+		{0x00,(0x0b << 3)|0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0},
+		{0x00,(0x0a << 3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0},
+		{0x00,(0x09 << 3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0},
+		{0x00,(0x0d << 3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x5, 0x0},
+		{0x00,(0x0e << 3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x6, 0x0},
+		{0x00,(0x04 << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0},
+		{0x00,(0x01 << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0},
+	}
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+	return copy_pirq_routing_table(addr, &intel_irq_routing_table);
+}
diff --git a/src/mainboard/asus/p2b/variants/p3b-f/overridetree.cb b/src/mainboard/asus/p2b/variants/p3b-f/overridetree.cb
new file mode 100644
index 0000000000..0a608121f6
--- /dev/null
+++ b/src/mainboard/asus/p2b/variants/p3b-f/overridetree.cb
@@ -0,0 +1,12 @@
+chip northbridge/intel/i440bx		# Northbridge
+	device domain 0 on		# PCI domain
+		chip southbridge/intel/i82371eb	# Southbridge
+			register "gpo" = "0x67ffbfff"	# GPIO: This value sets GPIOs 27,28 to expose HWM
+			device pci 4.0 on			# ISA bridge
+				chip superio/winbond/w83977tf	# Super I/O
+				device pnp 3f0.a off end	# ACPI
+				end
+			end
+		end
+	end
+end
diff --git a/src/mainboard/asus/p2b/variants/p3b-f/romstage.c b/src/mainboard/asus/p2b/variants/p3b-f/romstage.c
new file mode 100644
index 0000000000..437a38fded
--- /dev/null
+++ b/src/mainboard/asus/p2b/variants/p3b-f/romstage.c
@@ -0,0 +1,37 @@
+/* This file is part of the coreboot project. */
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <arch/io.h>
+#include <southbridge/intel/i82371eb/i82371eb.h>
+#include <northbridge/intel/i440bx/raminit.h>
+
+/*
+ * ASUS P3B-F specific SPD enable magic.
+ *
+ * Setting the byte at offset 0x37 in the PM I/O space to 0x6f will make the
+ * board DIMMs accessible at SMBus/SPD offsets 0x50-0x53. Per default the SPD
+ * offsets 0x50-0x53 are _not_ readable (all SPD reads will return 0xff) which
+ * will make RAM init fail.
+ *
+ * Tested values for PM I/O offset 0x37:
+ * 0x67: 11 00 111: Only SMBus/I2C offsets 0x48/0x49/0x2d accessible
+ * 0x6f: 11 01 111: Only SMBus/I2C offsets 0x50-0x53 (SPD) accessible
+ * 0x77: 11 10 111: Only SMBus/I2C offset 0x69 accessible
+ *
+ * PM I/O space offset 0x37 is GPOREG[31:24], i.e. it controls the GPIOs
+ * 24-30 of the PIIX4E (bit 31 is reserved). Thus, GPIOs 27 and 28
+ * control which SMBus/I2C offsets can be accessed.
+ */
+void enable_spd(void)
+{
+	outb(0x6f, PM_IO_BASE + 0x37);
+}
+
+/*
+ * Disable SPD access after RAM init to allow access to SMBus/I2C offsets
+ * 0x48/0x49/0x2d, which is required e.g. by lm-sensors.
+ */
+void disable_spd(void)
+{
+	outb(0x67, PM_IO_BASE + 0x37);
+}