asus/p2b-ls: Transform into variant

Boot tested on hardware.

Change-Id: I24afd67dada135a8c2597f5ac1c7e91ce43897c9
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39901
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

8 files changed, 0 insertions, 449 deletions

diff --git a/src/mainboard/asus/p2b-ls/Kconfig b/src/mainboard/asus/p2b-ls/Kconfig
deleted file mode 100644
index 2d12c86045..0000000000
--- a/src/mainboard/asus/p2b-ls/Kconfig
+++ /dev/null
@@ -1,39 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-if BOARD_ASUS_P2B_LS
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	select CPU_INTEL_SLOT_1
-	select NORTHBRIDGE_INTEL_I440BX
-	select SOUTHBRIDGE_INTEL_I82371EB
-	select SUPERIO_WINBOND_W83977TF
-	select HAVE_PIRQ_TABLE
-	select BOARD_ROMSIZE_KB_256
-	select SDRAMPWR_4DIMM
-	select HAVE_ACPI_TABLES
-
-config MAINBOARD_DIR
-	string
-	default "asus/p2b-ls"
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "P2B-LS"
-
-config IRQ_SLOT_COUNT
-	int
-	default 8
-
-endif # BOARD_ASUS_P2B_LS
diff --git a/src/mainboard/asus/p2b-ls/Kconfig.name b/src/mainboard/asus/p2b-ls/Kconfig.name
deleted file mode 100644
index 0ad0f4744c..0000000000
--- a/src/mainboard/asus/p2b-ls/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_ASUS_P2B_LS
-	bool "P2B-LS"
diff --git a/src/mainboard/asus/p2b-ls/acpi_tables.c b/src/mainboard/asus/p2b-ls/acpi_tables.c
deleted file mode 100644
index 9f18039c32..0000000000
--- a/src/mainboard/asus/p2b-ls/acpi_tables.c
+++ /dev/null
@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
-
-#include <arch/acpi.h>
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
-	/* mainboard has no ioapic */
-	return current;
-}
diff --git a/src/mainboard/asus/p2b-ls/board_info.txt b/src/mainboard/asus/p2b-ls/board_info.txt
deleted file mode 100644
index 21bf26e5ef..0000000000
--- a/src/mainboard/asus/p2b-ls/board_info.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Category: desktop
-Board URL: ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-ls/
-ROM package: DIP32
-ROM protocol: Parallel
-ROM socketed: y
-Flashrom support: y
-Release year: 1998
diff --git a/src/mainboard/asus/p2b-ls/devicetree.cb b/src/mainboard/asus/p2b-ls/devicetree.cb
deleted file mode 100644
index a9901b4198..0000000000
--- a/src/mainboard/asus/p2b-ls/devicetree.cb
+++ /dev/null
@@ -1,58 +0,0 @@
-chip northbridge/intel/i440bx		# Northbridge
-  device cpu_cluster 0 on		# APIC cluster
-    chip cpu/intel/slot_1		# CPU
-      device lapic 0 on end		# APIC
-    end
-  end
-  device domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    device pci 1.0 on end		# PCI/AGP bridge
-    chip southbridge/intel/i82371eb	# Southbridge
-      device pci 4.0 on			# ISA bridge
-        chip superio/winbond/w83977tf	# Super I/O (FIXME: It's W83977EF!)
-          device pnp 3f0.0 on		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 3f0.1 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-          end
-          device pnp 3f0.2 on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 3f0.3 on		# COM2 / IR
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 3f0.5 on		# PS/2 keyboard
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1		# PS/2 keyboard interrupt
-            irq 0x72 = 12		# PS/2 mouse interrupt
-          end
-          device pnp 3f0.7 on		# GPIO 1
-          end
-          device pnp 3f0.8 on		# GPIO 2
-          end
-          device pnp 3f0.a off		# ACPI
-          end
-        end
-      end
-      device pci 4.1 on	end		# IDE
-      device pci 4.2 on	end		# USB
-      device pci 4.3 on end		# ACPI
-      device pci 6.0 on end             # Onboard SCSI
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-      register "ide_legacy_enable" = "1"
-      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
-      register "ide0_drive0_udma33_enable" = "0"
-      register "ide0_drive1_udma33_enable" = "0"
-      register "ide1_drive0_udma33_enable" = "0"
-      register "ide1_drive1_udma33_enable" = "0"
-    end
-  end
-end
diff --git a/src/mainboard/asus/p2b-ls/dsdt.asl b/src/mainboard/asus/p2b-ls/dsdt.asl
deleted file mode 100644
index b49e0a1df0..0000000000
--- a/src/mainboard/asus/p2b-ls/dsdt.asl
+++ /dev/null
@@ -1,258 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
-
-#include <southbridge/intel/i82371eb/i82371eb.h>
-
-#define SUPERIO_PNP_BASE 0x3F0
-#define SUPERIO_SHOW_UARTA
-#define SUPERIO_SHOW_UARTB
-#define SUPERIO_SHOW_FDC
-#define SUPERIO_SHOW_LPT
-
-#include <arch/acpi.h>
-DefinitionBlock ("DSDT.aml", "DSDT", 2, OEM_ID, ACPI_TABLE_CREATOR, 1)
-{
-	/* \_SB scope defining the main processor is generated in SSDT. */
-
-	OperationRegion(X80, SystemIO, 0x80, 1)
-	Field(X80, ByteAcc, NoLock, Preserve)
-	{
-		P80, 8
-	}
-
-	/*
-	 * For now only define 2 power states:
-	 *  - S0 which is fully on
-	 *  - S5 which is soft off
-	 * Any others would involve declaring the wake up methods.
-	 */
-
-	/*
-	 * Intel 82371EB (PIIX4E) datasheet, section 7.2.3, page 142
-	 *
-	 * 0: soft off/suspend to disk					S5
-	 * 1: suspend to ram						S3
-	 * 2: powered on suspend, context lost				S2
-	 *    Note: 'context lost' means the CPU restarts at the reset
-	 *          vector
-	 * 3: powered on suspend, CPU context lost			S1
-	 *    Note: Looks like 'CPU context lost' does _not_ mean the
-	 *          CPU restarts at the reset vector. Most likely only
-	 *          caches are lost, so both 0x3 and 0x4 map to ACPI S1
-	 * 4: powered on suspend, context maintained			S1
-	 * 5: working (clock control)					S0
-	 * 6: reserved
-	 * 7: reserved
-	 */
-	Name (\_S0, Package () { 0x05, 0x05, 0x00, 0x00 })
-	/*
-	 * Kept as a memo of the value needed, but blocked out until
-	 * suspend/resume support is implemented.
-	 */
-	/*Name (\_S1, Package () { 0x04, 0x07, 0x00, 0x00 })*/
-	/*Name (\_S4, Package () { 0x01, 0x06, 0x00, 0x00 })*/
-	Name (\_S5, Package () { 0x00, 0x06, 0x00, 0x00 })
-
-	OperationRegion (GPOB, SystemIO, DEFAULT_PMBASE+DEVCTL, 0x10)
-	Field (GPOB, ByteAcc, NoLock, Preserve)
-	{
-		Offset (0x03),
-		TO12,   1, /* Device trap 12 */
-		Offset (0x08),
-		FANM,   1, /* GPO0, meant for fan */
-		Offset (0x09),
-		PLED,   1, /* GPO8, meant for power LED. Per PIIX4 datasheet */
-		    ,   3, /* this goes low when power is cut from its core. */
-		    ,   2,
-		    ,   16,
-		MSG0,   1 /* GPO30, message LED */
-	}
-
-	/* Prepare To Sleep, Arg0 is target S-state */
-	Method (\_PTS, 1, NotSerialized)
-	{
-		/* Disable fan, blink power LED, if not turning off */
-		If (LNotEqual (Arg0, 0x05))
-		{
-		    Store (Zero, FANM)
-		    Store (Zero, PLED)
-		}
-
-		/* Arms SMI for device 12 */
-		Store (One, TO12)
-		/* Put out a POST code */
-		Or (Arg0, 0xF0, P80)
-	}
-
-	Method (\_WAK, 1, NotSerialized)
-	{
-		/* Re-enable fan, stop power led blinking */
-		Store (One, FANM)
-		Store (One, PLED)
-		/* wake OK */
-		Return(Package(0x02){0x00, 0x00})
-	}
-
-	/* Root of the bus hierarchy */
-	Scope (\_SB)
-	{
-		Device (PWRB)
-		{
-			/* Power Button Device */
-			Name (_HID, EisaId ("PNP0C0C"))
-			Method (_STA, 0, NotSerialized)
-			{
-				Return (0x0B)
-			}
-		}
-		#include <southbridge/intel/i82371eb/acpi/intx.asl>
-
-		PCI_INTX_DEV(LNKA, \_SB.PCI0.PX40.PIRA, 1)
-		PCI_INTX_DEV(LNKB, \_SB.PCI0.PX40.PIRB, 2)
-		PCI_INTX_DEV(LNKC, \_SB.PCI0.PX40.PIRC, 3)
-		PCI_INTX_DEV(LNKD, \_SB.PCI0.PX40.PIRD, 4)
-
-		/* Top PCI device */
-		Device (PCI0)
-		{
-			Name (_HID, EisaId ("PNP0A03"))
-			Name (_UID, 0x00)
-			Name (_BBN, 0x00)
-
-			/* PCI Routing Table */
-			Name (_PRT, Package () {
-				Package (0x04) { 0x0001FFFF, 0, LNKA, 0 },
-				Package (0x04) { 0x0001FFFF, 1, LNKB, 0 },
-				Package (0x04) { 0x0001FFFF, 2, LNKC, 0 },
-				Package (0x04) { 0x0001FFFF, 3, LNKD, 0 },
-
-				Package (0x04) { 0x0004FFFF, 0, LNKA, 0 },
-				Package (0x04) { 0x0004FFFF, 1, LNKB, 0 },
-				Package (0x04) { 0x0004FFFF, 2, LNKC, 0 },
-				Package (0x04) { 0x0004FFFF, 3, LNKD, 0 },
-
-				Package (0x04) { 0x0006FFFF, 0, LNKD, 0 },
-				Package (0x04) { 0x0006FFFF, 1, LNKA, 0 },
-				Package (0x04) { 0x0006FFFF, 2, LNKB, 0 },
-				Package (0x04) { 0x0006FFFF, 3, LNKC, 0 },
-
-				Package (0x04) { 0x0009FFFF, 0, LNKD, 0 },
-				Package (0x04) { 0x0009FFFF, 1, LNKA, 0 },
-				Package (0x04) { 0x0009FFFF, 2, LNKB, 0 },
-				Package (0x04) { 0x0009FFFF, 3, LNKC, 0 },
-
-				Package (0x04) { 0x000AFFFF, 0, LNKC, 0 },
-				Package (0x04) { 0x000AFFFF, 1, LNKD, 0 },
-				Package (0x04) { 0x000AFFFF, 2, LNKA, 0 },
-				Package (0x04) { 0x000AFFFF, 3, LNKB, 0 },
-
-				Package (0x04) { 0x0007FFFF, 0, LNKC, 0 },
-				Package (0x04) { 0x0007FFFF, 1, LNKD, 0 },
-				Package (0x04) { 0x0007FFFF, 2, LNKA, 0 },
-				Package (0x04) { 0x0007FFFF, 3, LNKB, 0 },
-
-				Package (0x04) { 0x000BFFFF, 0, LNKB, 0 },
-				Package (0x04) { 0x000BFFFF, 1, LNKC, 0 },
-				Package (0x04) { 0x000BFFFF, 2, LNKD, 0 },
-				Package (0x04) { 0x000BFFFF, 3, LNKA, 0 },
-
-				Package (0x04) { 0x000CFFFF, 0, LNKA, 0 },
-				Package (0x04) { 0x000CFFFF, 1, LNKB, 0 },
-				Package (0x04) { 0x000CFFFF, 2, LNKC, 0 },
-				Package (0x04) { 0x000CFFFF, 3, LNKD, 0 },
-
-			})
-			#include <northbridge/intel/i440bx/acpi/sb_pci0_crs.asl>
-
-			/* Begin southbridge block */
-			Device (PX40)
-			{
-				Name(_ADR, 0x00040000)
-				OperationRegion (PIRQ, PCI_Config, 0x60, 0x04)
-				Field (PIRQ, ByteAcc, NoLock, Preserve)
-				{
-					PIRA,   8,
-					PIRB,   8,
-					PIRC,   8,
-					PIRD,   8
-				}
-
-				/* PNP Motherboard Resources */
-				Device (SYSR)
-				{
-					Name (_HID, EisaId ("PNP0C02"))
-					Method (_CRS, 0, NotSerialized)
-					{
-					Name (BUF1, ResourceTemplate ()
-					{
-						/* PM register ports */
-						IO (Decode16, 0x0000, 0x0000, 0x01, 0x40, _Y06)
-						/* SMBus register ports */
-						IO (Decode16, 0x0000, 0x0000, 0x01, 0x10, _Y07)
-						/* PIIX4E ports */
-						/* Aliased DMA ports */
-						IO (Decode16, 0x0010, 0x0010, 0x01, 0x10, )
-						/* Aliased PIC ports */
-						IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E, )
-						/* Aliased timer ports */
-						IO (Decode16, 0x0050, 0x0050, 0x01, 0x04, )
-						IO (Decode16, 0x0062, 0x0062, 0x01, 0x02, )
-						IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B, )
-						IO (Decode16, 0x0074, 0x0074, 0x01, 0x0C, )
-						IO (Decode16, 0x0091, 0x0091, 0x01, 0x03, )
-						IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E, )
-						IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10, )
-						IO (Decode16, 0x0294, 0x0294, 0x01, 0x04, )
-						IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x02, )
-						IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02, )
-					})
-					CreateWordField (BUF1, _Y06._MIN, PMLO)
-					CreateWordField (BUF1, _Y06._MAX, PMRL)
-					CreateWordField (BUF1, _Y07._MIN, SBLO)
-					CreateWordField (BUF1, _Y07._MAX, SBRL)
-
-					And (\_SB.PCI0.PX43.PM00, 0xFFFE, PMLO)
-					And (\_SB.PCI0.PX43.SB00, 0xFFFE, SBLO)
-					Store (PMLO, PMRL)
-					Store (SBLO, SBRL)
-					Return (BUF1)
-					}
-				}
-				#include <southbridge/intel/i82371eb/acpi/i82371eb.asl>
-			}
-			Device (PX43)
-			{
-				Name (_ADR, 0x00040003)  // _ADR: Address
-				OperationRegion (IPMU, PCI_Config, PMBA, 0x02)
-				Field (IPMU, ByteAcc, NoLock, Preserve)
-				{
-				    PM00,   16
-				}
-
-				OperationRegion (ISMB, PCI_Config, SMBBA, 0x02)
-				Field (ISMB, ByteAcc, NoLock, Preserve)
-				{
-				    SB00,   16
-				}
-			}
-
-			#include <superio/winbond/w83977tf/acpi/superio.asl>
-		}
-	}
-
-	/* ACPI Message */
-	Scope (\_SI)
-	{
-		Method (_MSG, 1, NotSerialized)
-		{
-			If (LEqual (Arg0, Zero))
-			{
-				Store (One, MSG0)
-			}
-			Else
-			{
-				Store (Zero, MSG0)
-			}
-		}
-	}
-}
diff --git a/src/mainboard/asus/p2b-ls/irq_tables.c b/src/mainboard/asus/p2b-ls/irq_tables.c
deleted file mode 100644
index b7536eb397..0000000000
--- a/src/mainboard/asus/p2b-ls/irq_tables.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/pirq_routing.h>
-
-static const struct irq_routing_table intel_irq_routing_table = {
-	PIRQ_SIGNATURE,
-	PIRQ_VERSION,
-	32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
-	0x00,			/* Interrupt router bus */
-	(0x04 << 3) | 0x0,	/* Interrupt router device */
-	0,			/* IRQs devoted exclusively to PCI usage */
-	0x8086,			/* Vendor */
-	0x122e,			/* Device */
-	0,			/* Miniport */
-	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
-	0x10,			/* Checksum (has to be set to some value that
-				 * would give 0 after the sum of all bytes
-				 * for this structure (including checksum).
-				 */
-	{
-		/* bus,        dev | fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
-		{0x00, (0x0c << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x1, 0x0},
-		{0x00, (0x0b << 3) | 0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}}, 0x2, 0x0},
-		{0x00, (0x0a << 3) | 0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}}, 0x3, 0x0},
-		{0x00, (0x09 << 3) | 0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}}, 0x4, 0x0},
-		{0x00, (0x04 << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x0, 0x0},
-		{0x00, (0x01 << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x0, 0x0},
-		{0x00, (0x06 << 3) | 0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}}, 0x0, 0x0},
-		{0x00, (0x07 << 3) | 0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}}, 0x0, 0x0},
-	}
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/asus/p2b-ls/romstage.c b/src/mainboard/asus/p2b-ls/romstage.c
deleted file mode 100644
index 546d9ed419..0000000000
--- a/src/mainboard/asus/p2b-ls/romstage.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <northbridge/intel/i440bx/raminit.h>
-#include <superio/winbond/common/winbond.h>
-/* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */
-#include <superio/winbond/w83977tf/w83977tf.h>
-
-#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
-
-void mainboard_enable_serial(void)
-{
-	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-}