Add ASUS M4A785T-M mainboard support

This mainboard is very similar to the M4A785-M, but it has
  DDR3 instead of DDR2.

That's why most of the code was copied or included from
  the m4a785-m directory

Notable changes between the two mainboards include:
 * the selection of the last microcode (mc_patch_010000b6.h)
   which made it pass the CPU init.
 * the selection of DDR3 which made it pass the ram init

This change was tested with the Trisquel 5.0 GNU/Linux distribution
  which uses the linux-libre version 2.6.38-12-generic

The mainboard boots fine, however some special care is required for
  the onboard sound CODEC, and the onboard video chip:
  * the onboard sound CODEC(snd-hda-* has to be blacklisted), the issue
    is the same than the ASUS M4A785-M mainboard:
    It causes a flood of interupts which prevents booting
  * The internal video chip currently requires pci=nocrs, else
    the graphics are frozen as soon as the radeon module loads,
    and dmesg would print the following(the card only has 256M,
    and the mainboard was equiped with 2G of RAM):
      [    3.674762] [drm] radeon: 3584M of VRAM memory ready
      [    3.679863] [drm] radeon: 512M of GTT memory ready.
    instead of :
      [   45.876088] [drm] radeon: 256M of VRAM memory ready
      [   45.876089] [drm] radeon: 512M of GTT memory ready.
  * The screen(both VGA and HDMI) flickers at high resolution
  * Sometimes the computer freeze while changing the resolution
    (even the serial console stops responding)

The following peripherals were tested:
 * The ath9k PCI wireless card was tested
 * The SATA hard disk works fine
 * the USB keyboard and mouse work fine
 * htop see 2 cores
 * serial port works under coreboot and GNU/Linux
 * power off and reboot works

CPU frequency cannot be changed yet, this is addressed
  in a new commit.

More detail are available here:
  http://www.coreboot.org/ASUS_M4A785T-M

dmesg is available here:
  http://www.coreboot.org/pipermail/coreboot/2011-November/067604.html

The mailing list thread on the graphic problem is here:
  http://www.coreboot.org/pipermail/coreboot/2011-November/067466.html

Change-Id: I5df0bc1f9f0071b1e1ee7c8a356bf517aa8cf732
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/457
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

1 files changed, 75 insertions, 0 deletions

diff --git a/src/mainboard/asus/m4a785t-m/acpi/cpstate.asl b/src/mainboard/asus/m4a785t-m/acpi/cpstate.asl
new file mode 100644
index 0000000000..6a1b002474
--- /dev/null
+++ b/src/mainboard/asus/m4a785t-m/acpi/cpstate.asl
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* This file defines the processor and performance state capability
+ * for each core in the system.  It is included into the DSDT for each
+ * core.  It assumes that each core of the system has the same performance
+ * characteristics.
+*/
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001)
+	{
+		Scope (\_PR) {
+		Processor(CPU0,0,0x808,0x06) {
+			#include "cpstate.asl"
+		}
+		Processor(CPU1,1,0x0,0x0) {
+			#include "cpstate.asl"
+		}
+		Processor(CPU2,2,0x0,0x0) {
+			#include "cpstate.asl"
+		}
+		Processor(CPU3,3,0x0,0x0) {
+			#include "cpstate.asl"
+		}
+	}
+*/
+	/* P-state support: The maximum number of P-states supported by the */
+	/* CPUs we'll use is 6. */
+	/* Get from AMI BIOS. */
+	Name(_PSS, Package(){
+		Package ()
+		{
+		    0x00000AF0,
+		    0x0000BF81,
+		    0x00000002,
+		    0x00000002,
+		    0x00000000,
+		    0x00000000
+		},
+
+		Package ()
+		{
+		    0x00000578,
+		    0x000076F2,
+		    0x00000002,
+		    0x00000002,
+		    0x00000001,
+		    0x00000001
+		}
+	})
+
+	Name(_PCT, Package(){
+		ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
+		ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
+	})
+
+	Method(_PPC, 0){
+		Return(0)
+	}