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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-07-03 06:50:19 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-07-04 04:14:22 +0000 |
| commit | 04d025cf5015b06f9e4dafc7092cfbd5d24b241e (patch) | |
| tree | 05c5b7a4b4931faed61dfb84b86a759810f99be2 /src/mainboard/asus/kgpe-d16/romstage.c | |
| parent | 8560db611608cbe0e344c1a301cf23e4c1fb36c8 (diff) | |
amdfam10: Declare get_sysinfo()
It's forbidden to use dereference CAR_GLOBAL variables
directly. The notation fails after CAR teardown for
romstage.
Change-Id: I6e6285ca0f520608c2a344517fbac943aeb36d87
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33995
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/asus/kgpe-d16/romstage.c')
| -rw-r--r-- | src/mainboard/asus/kgpe-d16/romstage.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index 85ad0b6f64..637ec42109 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -52,7 +52,6 @@ #define SERIAL_1_DEV PNP_DEV(0x2e, W83667HG_A_SP2) int spd_read_byte(unsigned int device, unsigned int address); -extern struct sys_info sysinfo_car; int spd_read_byte(unsigned int device, unsigned int address) { @@ -180,7 +179,7 @@ static const uint8_t spd_addr_fam10[] = { void activate_spd_rom(const struct mem_controller *ctrl) { - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); printk(BIOS_DEBUG, "activate_spd_rom() for node %02x\n", ctrl->node_id); if (ctrl->node_id == 0) { printk(BIOS_DEBUG, "enable_spd_node0()\n"); @@ -467,7 +466,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) : "=r" (esp) ); - struct sys_info *sysinfo = &sysinfo_car; + struct sys_info *sysinfo = get_sysinfo(); /* Limit the maximum HT speed to 2.6GHz to prevent lockups * due to HT CPU <--> CPU wiring not being validated to 3.2GHz |