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authorAngel Pons <th3fanbus@gmail.com>2021-05-17 13:03:36 +0200
committerPatrick Georgi <pgeorgi@google.com>2021-05-18 11:51:02 +0000
commit9d54a228092e627ad7f159bb21e45c468c2f9f2c (patch)
tree1909eb5bcf8b25a2d7aa027ded23bf7db6fd74f7 /src/mainboard/asus/h61-series
parent14b7e655bf876e8389bc83bc30e702ca3c58e845 (diff)
mb/asus/h61m-cs: Transform into variant setup
To preserve reproducibility, temporarily guard mainboard.c contents. This will be removed once all boards have become variants. Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus H61M-CS remains identical when not adding the .config file in it. Change-Id: I1ffb41470d24713a4a7f0689958b733d4b1bdf52 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/asus/h61-series')
-rw-r--r--src/mainboard/asus/h61-series/Kconfig2
-rw-r--r--src/mainboard/asus/h61-series/Kconfig.name10
-rw-r--r--src/mainboard/asus/h61-series/mainboard.c20
-rw-r--r--src/mainboard/asus/h61-series/variants/h61m-cs/board_info.txt6
-rw-r--r--src/mainboard/asus/h61-series/variants/h61m-cs/cmos.default6
-rw-r--r--src/mainboard/asus/h61-series/variants/h61m-cs/cmos.layout66
-rw-r--r--src/mainboard/asus/h61-series/variants/h61m-cs/data.vbtbin0 -> 3902 bytes
-rw-r--r--src/mainboard/asus/h61-series/variants/h61m-cs/devicetree.cb87
-rw-r--r--src/mainboard/asus/h61-series/variants/h61m-cs/early_init.c43
-rw-r--r--src/mainboard/asus/h61-series/variants/h61m-cs/gma-mainboard.ads13
-rw-r--r--src/mainboard/asus/h61-series/variants/h61m-cs/gpio.c217
-rw-r--r--src/mainboard/asus/h61-series/variants/h61m-cs/hda_verb.c29
12 files changed, 499 insertions, 0 deletions
diff --git a/src/mainboard/asus/h61-series/Kconfig b/src/mainboard/asus/h61-series/Kconfig
index 959580f48e..212c06b33d 100644
--- a/src/mainboard/asus/h61-series/Kconfig
+++ b/src/mainboard/asus/h61-series/Kconfig
@@ -19,11 +19,13 @@ config MAINBOARD_DIR
config VARIANT_DIR
string
+ default "h61m-cs" if BOARD_ASUS_H61M_CS
default "p8h61-m_lx3_r2_0" if BOARD_ASUS_P8H61_M_LX3_R2_0
default "p8h61-m_pro" if BOARD_ASUS_P8H61_M_PRO
config MAINBOARD_PART_NUMBER
string
+ default "H61M-CS" if BOARD_ASUS_H61M_CS
default "P8H61-M LX3 R2.0" if BOARD_ASUS_P8H61_M_LX3_R2_0
default "P8H61-M PRO" if BOARD_ASUS_P8H61_M_PRO
diff --git a/src/mainboard/asus/h61-series/Kconfig.name b/src/mainboard/asus/h61-series/Kconfig.name
index d876aea3b7..6bb8d45743 100644
--- a/src/mainboard/asus/h61-series/Kconfig.name
+++ b/src/mainboard/asus/h61-series/Kconfig.name
@@ -1,3 +1,13 @@
+config BOARD_ASUS_H61M_CS
+ bool "H61M-CS"
+ select BOARD_ASUS_H61_SERIES
+ select BOARD_ROMSIZE_KB_8192
+ select HAVE_CMOS_DEFAULT
+ select HAVE_OPTION_TABLE
+ select INTEL_INT15
+ select NO_UART_ON_SUPERIO
+ select SUPERIO_NUVOTON_NCT6779D
+
config BOARD_ASUS_P8H61_M_LX3_R2_0
bool "P8H61-M LX3 R2.0"
select BOARD_ASUS_H61_SERIES
diff --git a/src/mainboard/asus/h61-series/mainboard.c b/src/mainboard/asus/h61-series/mainboard.c
new file mode 100644
index 0000000000..48fcdce34e
--- /dev/null
+++ b/src/mainboard/asus/h61-series/mainboard.c
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* TODO: remove */
+#if CONFIG(INTEL_INT15)
+
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+
+static void mainboard_enable(struct device *dev)
+{
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,
+ GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
+
+#endif
diff --git a/src/mainboard/asus/h61-series/variants/h61m-cs/board_info.txt b/src/mainboard/asus/h61-series/variants/h61m-cs/board_info.txt
new file mode 100644
index 0000000000..d16d93036e
--- /dev/null
+++ b/src/mainboard/asus/h61-series/variants/h61m-cs/board_info.txt
@@ -0,0 +1,6 @@
+Category: desktop
+Board URL: https://www.asus.com/in/Motherboards/H61MCS
+ROM package: DIP-8
+ROM protocol: SPI
+ROM socketed: y
+Flashrom support: y
diff --git a/src/mainboard/asus/h61-series/variants/h61m-cs/cmos.default b/src/mainboard/asus/h61-series/variants/h61m-cs/cmos.default
new file mode 100644
index 0000000000..c1b9aa98f1
--- /dev/null
+++ b/src/mainboard/asus/h61-series/variants/h61m-cs/cmos.default
@@ -0,0 +1,6 @@
+boot_option=Fallback
+debug_level=Debug
+power_on_after_fail=Disable
+nmi=Enable
+sata_mode=AHCI
+gfx_uma_size=32M
diff --git a/src/mainboard/asus/h61-series/variants/h61m-cs/cmos.layout b/src/mainboard/asus/h61-series/variants/h61m-cs/cmos.layout
new file mode 100644
index 0000000000..8c6a055ca3
--- /dev/null
+++ b/src/mainboard/asus/h61-series/variants/h61m-cs/cmos.layout
@@ -0,0 +1,66 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395 4 e 6 debug_level
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+
+421 1 e 9 sata_mode
+
+# coreboot config options: cpu
+
+# coreboot config options: northbridge
+432 3 e 11 gfx_uma_size
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+4 0 Fallback
+4 1 Normal
+6 0 Emergency
+6 1 Alert
+6 2 Critical
+6 3 Error
+6 4 Warning
+6 5 Notice
+6 6 Info
+6 7 Debug
+6 8 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+9 0 AHCI
+9 1 IDE
+11 0 32M
+11 1 64M
+11 2 96M
+11 3 128M
+11 4 160M
+11 5 192M
+11 6 224M
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 439 984
diff --git a/src/mainboard/asus/h61-series/variants/h61m-cs/data.vbt b/src/mainboard/asus/h61-series/variants/h61m-cs/data.vbt
new file mode 100644
index 0000000000..16e13f2b40
--- /dev/null
+++ b/src/mainboard/asus/h61-series/variants/h61m-cs/data.vbt
Binary files differ
diff --git a/src/mainboard/asus/h61-series/variants/h61m-cs/devicetree.cb b/src/mainboard/asus/h61-series/variants/h61m-cs/devicetree.cb
new file mode 100644
index 0000000000..3ec5e5fa28
--- /dev/null
+++ b/src/mainboard/asus/h61-series/variants/h61m-cs/devicetree.cb
@@ -0,0 +1,87 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/sandybridge
+ device cpu_cluster 0 on
+ chip cpu/intel/model_206ax
+ register "acpi_c1" = "1"
+ register "acpi_c2" = "3"
+ register "acpi_c3" = "5"
+ device lapic 0x0 on end
+ device lapic 0xacac off end
+ end
+ end
+ device domain 0 on
+ subsystemid 0x1043 0x844d inherit
+ device pci 00.0 on end # Host bridge
+ device pci 01.0 on end # PCIe Bridge for discrete graphics
+ device pci 02.0 on end # Internal graphics
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "c2_latency" = "0x0065"
+ register "gen1_dec" = "0x000c0291"
+ register "sata_port_map" = "0x33"
+ register "spi_lvscc" = "0x2005"
+ register "spi_uvscc" = "0x2005"
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT
+ device pci 19.0 off end # Intel Gigabit Ethernet
+ device pci 1a.0 on end # USB2 EHCI #2
+ device pci 1b.0 on # High Definition Audio Audio controller
+ subsystemid 0x1043 0x8445
+ end
+ device pci 1c.0 off end # PCIe Port #1
+ device pci 1c.1 off end # PCIe Port #2
+ device pci 1c.2 off end # PCIe Port #3
+ device pci 1c.3 on end # PCIe x1 Slot 1 PCIE_1
+ device pci 1c.4 on end # PCIe x1 Slot 2 PCIE_2
+ device pci 1c.5 on # Realtek Gigabit NIC
+ device pci 00.0 on end
+ end
+ device pci 1c.6 off end # PCIe Port #7
+ device pci 1c.7 off end # PCIe Port #8
+ device pci 1d.0 on end # USB2 EHCI #1
+ device pci 1e.0 off end # PCI bridge
+ device pci 1f.0 on # LPC bridge PCI-LPC bridge
+ chip superio/nuvoton/nct6779d
+ device pnp 2e.1 off end # Parallel
+ device pnp 2e.2 off end # UART A
+ device pnp 2e.3 off end # UART B, IR
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x0060
+ io 0x62 = 0x0064
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off end # CIR
+ device pnp 2e.7 off end # GPIO6-8
+ device pnp 2e.8 off end # WDT1, GPIO0, GPIO1
+ device pnp 2e.108 off end # GPIO0
+ device pnp 2e.9 off end # GPIO1-8
+ device pnp 2e.109 on end # GPIO1
+ device pnp 2e.209 on end # GPIO2
+ device pnp 2e.309 on end # GPIO3
+ device pnp 2e.409 off end # GPIO4
+ device pnp 2e.509 on end # GPIO5
+ device pnp 2e.609 off end # GPIO6
+ device pnp 2e.709 off end # GPIO7
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # H/W Monitor, FP LED
+ io 0x60 = 0x0290
+ io 0x62 = 0
+ irq 0x70 = 0
+ end
+ device pnp 2e.d off end # WDT1
+ device pnp 2e.e off end # CIR WAKE-UP
+ device pnp 2e.f off end # GPIO Push-pull/Open-drain selection
+ device pnp 2e.14 off end # PORT80 UART
+ device pnp 2e.16 off end # Deep Sleep
+ end
+ end
+ device pci 1f.2 on end # SATA Controller 1
+ device pci 1f.3 on end # SMBus
+ device pci 1f.5 off end # SATA Controller 2
+ device pci 1f.6 off end # Thermal
+ end
+ end
+end
diff --git a/src/mainboard/asus/h61-series/variants/h61m-cs/early_init.c b/src/mainboard/asus/h61-series/variants/h61m-cs/early_init.c
new file mode 100644
index 0000000000..cb8daaf014
--- /dev/null
+++ b/src/mainboard/asus/h61-series/variants/h61m-cs/early_init.c
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pnp_ops.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct6779d/nct6779d.h>
+
+#define SIO_PORT 0x2e
+#define SIO_DEV PNP_DEV(SIO_PORT, 0)
+#define ACPI_DEV PNP_DEV(SIO_PORT, NCT6779D_ACPI)
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 0, 0 },
+ { 1, 0, 0 },
+ { 1, 0, 1 },
+ { 1, 0, 1 },
+ { 1, 0, 2 },
+ { 1, 0, 2 },
+ { 1, 0, 3 },
+ { 1, 0, 3 },
+ { 1, 0, 4 },
+ { 1, 0, 4 },
+ { 1, 0, 6 },
+ { 1, 0, 5 },
+ { 1, 0, 5 },
+ { 1, 0, 6 },
+};
+
+void bootblock_mainboard_early_init(void)
+{
+ nuvoton_pnp_enter_conf_state(SIO_DEV);
+ pnp_set_logical_device(ACPI_DEV);
+ pnp_write_config(ACPI_DEV, 0xe4, 0x10);
+ nuvoton_pnp_exit_conf_state(SIO_DEV);
+}
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+ read_spd(&spd[0], 0x50, id_only);
+ read_spd(&spd[2], 0x52, id_only);
+}
diff --git a/src/mainboard/asus/h61-series/variants/h61m-cs/gma-mainboard.ads b/src/mainboard/asus/h61-series/variants/h61m-cs/gma-mainboard.ads
new file mode 100644
index 0000000000..f07946ae2d
--- /dev/null
+++ b/src/mainboard/asus/h61-series/variants/h61m-cs/gma-mainboard.ads
@@ -0,0 +1,13 @@
+-- SPDX-License-Identifier: GPL-2.0-only
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+ ports : constant Port_List :=
+ (Analog,
+ others => Disabled);
+end GMA.Mainboard;
diff --git a/src/mainboard/asus/h61-series/variants/h61m-cs/gpio.c b/src/mainboard/asus/h61-series/variants/h61m-cs/gpio.c
new file mode 100644
index 0000000000..39b7effffe
--- /dev/null
+++ b/src/mainboard/asus/h61-series/variants/h61m-cs/gpio.c
@@ -0,0 +1,217 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_GPIO,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_GPIO,
+ .gpio11 = GPIO_MODE_GPIO,
+ .gpio12 = GPIO_MODE_GPIO,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_GPIO,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_GPIO,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_GPIO,
+ .gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_OUTPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio5 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_OUTPUT,
+ .gpio10 = GPIO_DIR_INPUT,
+ .gpio11 = GPIO_DIR_INPUT,
+ .gpio12 = GPIO_DIR_OUTPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio20 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio23 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_INPUT,
+ .gpio29 = GPIO_DIR_INPUT,
+ .gpio30 = GPIO_DIR_INPUT,
+ .gpio31 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio0 = GPIO_LEVEL_LOW,
+ .gpio8 = GPIO_LEVEL_HIGH,
+ .gpio12 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_GPIO,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_GPIO,
+ .gpio42 = GPIO_MODE_GPIO,
+ .gpio43 = GPIO_MODE_GPIO,
+ .gpio44 = GPIO_MODE_GPIO,
+ .gpio45 = GPIO_MODE_GPIO,
+ .gpio46 = GPIO_MODE_GPIO,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_GPIO,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_GPIO,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_GPIO,
+ .gpio56 = GPIO_MODE_NATIVE,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_GPIO,
+ .gpio59 = GPIO_MODE_GPIO,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_GPIO,
+ .gpio62 = GPIO_MODE_GPIO,
+ .gpio63 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio32 = GPIO_DIR_INPUT,
+ .gpio33 = GPIO_DIR_INPUT,
+ .gpio34 = GPIO_DIR_INPUT,
+ .gpio35 = GPIO_DIR_INPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio41 = GPIO_DIR_INPUT,
+ .gpio42 = GPIO_DIR_INPUT,
+ .gpio43 = GPIO_DIR_INPUT,
+ .gpio44 = GPIO_DIR_INPUT,
+ .gpio45 = GPIO_DIR_INPUT,
+ .gpio46 = GPIO_DIR_INPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_INPUT,
+ .gpio50 = GPIO_DIR_INPUT,
+ .gpio51 = GPIO_DIR_INPUT,
+ .gpio52 = GPIO_DIR_INPUT,
+ .gpio53 = GPIO_DIR_INPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+ .gpio55 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio58 = GPIO_DIR_INPUT,
+ .gpio59 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_INPUT,
+ .gpio61 = GPIO_DIR_INPUT,
+ .gpio62 = GPIO_DIR_INPUT,
+ .gpio63 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio63 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+ .gpio63 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_GPIO,
+ .gpio65 = GPIO_MODE_GPIO,
+ .gpio66 = GPIO_MODE_GPIO,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_GPIO,
+ .gpio71 = GPIO_MODE_GPIO,
+ .gpio72 = GPIO_MODE_GPIO,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_GPIO,
+ .gpio75 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio64 = GPIO_DIR_INPUT,
+ .gpio65 = GPIO_DIR_INPUT,
+ .gpio66 = GPIO_DIR_INPUT,
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio70 = GPIO_DIR_INPUT,
+ .gpio71 = GPIO_DIR_INPUT,
+ .gpio72 = GPIO_DIR_INPUT,
+ .gpio74 = GPIO_DIR_INPUT,
+ .gpio75 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/asus/h61-series/variants/h61m-cs/hda_verb.c b/src/mainboard/asus/h61-series/variants/h61m-cs/hda_verb.c
new file mode 100644
index 0000000000..0a3a75c5db
--- /dev/null
+++ b/src/mainboard/asus/h61-series/variants/h61m-cs/hda_verb.c
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <stdint.h>
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x10ec0887, /* Codec Vendor / Device ID: Realtek */
+ 0x10438445, /* Subsystem ID */
+ 15, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(0, 0x10438445),
+ AZALIA_PIN_CFG(0, 0x11, 0x40330000),
+ AZALIA_PIN_CFG(0, 0x12, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x14, 0x01014010),
+ AZALIA_PIN_CFG(0, 0x15, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x18, 0x01a19030),
+ AZALIA_PIN_CFG(0, 0x19, 0x02a19040),
+ AZALIA_PIN_CFG(0, 0x1a, 0x0181303f),
+ AZALIA_PIN_CFG(0, 0x1b, 0x02214020),
+ AZALIA_PIN_CFG(0, 0x1c, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1d, 0x4024c601),
+ AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;