diff options
| author | Kevin Paul Herbert <kph@meraki.net> | 2014-12-24 18:43:20 -0800 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2015-02-15 08:50:22 +0100 |
| commit | bde6d309dfafe58732ec46314a2d4c08974b62d4 (patch) | |
| tree | 17ba00565487ddfbb5759c96adfbb3fffe2a4550 /src/mainboard/asus/dsbf | |
| parent | 4b10dec1a66122b515b2191f823d7fd379ec655f (diff) | |
x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer
On x86, change the type of the address parameter in
read8()/read16/read32()/write8()/write16()/write32() to be a
pointer, instead of unsigned long.
Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7784
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/asus/dsbf')
| -rw-r--r-- | src/mainboard/asus/dsbf/devicetree.cb | 4 | ||||
| -rw-r--r-- | src/mainboard/asus/dsbf/romstage.c | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/asus/dsbf/devicetree.cb b/src/mainboard/asus/dsbf/devicetree.cb index b4d1b63ff8..0d3b6c8249 100644 --- a/src/mainboard/asus/dsbf/devicetree.cb +++ b/src/mainboard/asus/dsbf/devicetree.cb @@ -91,13 +91,13 @@ chip northbridge/intel/i5000 register "have_isa_interrupts" = "1" register "irq_on_fsb" = "1" register "enable_virtual_wire" = "1" - register "base" = "0xfec00000" + register "base" = "(void *)0xfec00000" device ioapic 8 on end end chip drivers/generic/ioapic register "irq_on_fsb" = "1" - register "base" = "0xfec80000" + register "base" = "(void *)0xfec80000" device ioapic 9 on end end diff --git a/src/mainboard/asus/dsbf/romstage.c b/src/mainboard/asus/dsbf/romstage.c index d7bcb89554..699aae1289 100644 --- a/src/mainboard/asus/dsbf/romstage.c +++ b/src/mainboard/asus/dsbf/romstage.c @@ -49,7 +49,7 @@ static void early_config(void) u32 gcs, rpc, fd; /* Enable RCBA */ - pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, DEFAULT_RCBA | 1); + pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); /* Disable watchdog */ gcs = read32(DEFAULT_RCBA + RCBA_GCS); @@ -138,7 +138,7 @@ void main(unsigned long bist) smbus_write_byte(0x6f, 0x08, 0x06); smbus_write_byte(0x6f, 0x09, 0x00); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, DEFAULT_RCBA | 1); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, (uintptr_t)DEFAULT_RCBA | 1); i5000_fbdimm_init(); smbus_write_byte(0x69, 0x01, 0x01); } |