mainboard/asus/am1i-a: add support for board ASUS AM1I-A

Add code to support the board ASUS AM1I-A. Tested with multiple payloads
and OSes with satisfactory results. S3 suspend/resume works fine with
Linux but has issues with Windows (an exception is thrown). However,
after manually rebooting, Windows resumes the suspended session.

* Tested with: SeaBIOS 1.11 + Linux 4.10 - OK
* Tested with: tianocore vEDK2017 + MS Windows 8.1 - OK
* Tested with: FILO 0.6.0 - hangs after showing the banner

Details are going to be published on the board's status page.

Change-Id: I3d9432849560df81536bbb2ce4c87cd265b820f7
Signed-off-by: Gergely Kiss <mail.gery@gmail.com>
Reviewed-on: https://review.coreboot.org/23002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

6 files changed, 558 insertions, 0 deletions

diff --git a/src/mainboard/asus/am1i-a/acpi/mainboard.asl b/src/mainboard/asus/am1i-a/acpi/mainboard.asl
new file mode 100644
index 0000000000..68609d868e
--- /dev/null
+++ b/src/mainboard/asus/am1i-a/acpi/mainboard.asl
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* Memory related values */
+Name(LOMH, 0x0)	/* Start of unused memory in C0000-E0000 range */
+Name(PBAD, 0x0)	/* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+Name(PBLN, 0x0)	/* Length of BIOS area */
+
+Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS)	/* Base address of PCIe config space */
+Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
+Name(HPBA, 0xFED00000)	/* Base address of HPET table */
+
+/* Some global data */
+Name(OSVR, 3)	/* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
+Name(OSV, Ones)	/* Assume nothing */
+Name(PMOD, One)	/* Assume APIC */
+
+/* AcpiGpe0Blk */
+OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)
+	Field(GP0B, ByteAcc, NoLock, Preserve) {
+	, 11,
+	USBS, 1,
+}
diff --git a/src/mainboard/asus/am1i-a/acpi/routing.asl b/src/mainboard/asus/am1i-a/acpi/routing.asl
new file mode 100644
index 0000000000..76d1c47344
--- /dev/null
+++ b/src/mainboard/asus/am1i-a/acpi/routing.asl
@@ -0,0 +1,165 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ * Copyright (C) 2018 Gergely Kiss <mail.gery@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* Routing is in System Bus scope */
+Name(PR0, Package(){
+	/* NB devices */
+	/* Bus 0, Dev 0 - F16 Host Controller */
+
+	/* Bus 0, Dev 1, Func 0 - PCI Bridge for Internal Graphics(IGP) */
+	/* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */
+	Package(){0x0001FFFF, 0, INTA, 0 },
+	Package(){0x0001FFFF, 1, INTB, 0 },
+
+	/* Bus 0, Dev 2 - PCIe Bridges */
+	Package(){0x0002FFFF, 0, INTA, 0 },
+	Package(){0x0002FFFF, 1, INTB, 0 },
+	Package(){0x0002FFFF, 2, INTC, 0 },
+	Package(){0x0002FFFF, 3, INTD, 0 },
+
+	/* FCH devices */
+	/* Bus 0, Dev 14 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
+	Package(){0x0014FFFF, 0, INTA, 0 },
+	Package(){0x0014FFFF, 1, INTB, 0 },
+	Package(){0x0014FFFF, 2, INTC, 0 },
+	Package(){0x0014FFFF, 3, INTD, 0 },
+
+	/* Bus 0, Dev 12 Func 0 - USB: OHCI */
+	/* Bus 0, Dev 12 Func 2 - USB: EHCI */
+	Package(){0x0012FFFF, 0, INTC, 0 },
+	Package(){0x0012FFFF, 1, INTB, 0 },
+
+	/* Bus 0, Dev 13 Func 0 - USB: OHCI */
+	/* Bus 0, Dev 13 Func 2 - USB: EHCI */
+	Package(){0x0013FFFF, 0, INTC, 0 },
+	Package(){0x0013FFFF, 1, INTB, 0 },
+
+	/* Bus 0, Dev 10 Func 0 - USB: XHCI */
+	Package(){0x0010FFFF, 0, INTC, 0 },
+
+	/* Bus 0, Dev 11 - SATA controller */
+	Package(){0x0011FFFF, 0, INTD, 0 },
+})
+
+Name(APR0, Package(){
+	/* NB devices in APIC mode */
+	/* Bus 0, Dev 0 - F16 Host Controller */
+
+	/* Bus 0, Dev 1, Func 0 - PCI Bridge for Internal Graphics(IGP) */
+	/* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */
+	Package(){0x0001FFFF, 0, 0, 16 },
+	Package(){0x0001FFFF, 1, 0, 17 },
+
+	/* Bus 0, Dev 2 - PCIe Bridges  */
+	Package(){0x0002FFFF, 0, 0, 16 },
+	Package(){0x0002FFFF, 1, 0, 17 },
+	Package(){0x0002FFFF, 2, 0, 18 },
+	Package(){0x0002FFFF, 3, 0, 19 },
+
+	/* SB devices in APIC mode */
+	/* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
+	Package(){0x0014FFFF, 0, 0, 16 },
+	Package(){0x0014FFFF, 1, 0, 17 },
+	Package(){0x0014FFFF, 2, 0, 18 },
+	Package(){0x0014FFFF, 3, 0, 19 },
+
+	/* Bus 0, Dev 12 Func 0 - USB: OHCI */
+	/* Bus 0, Dev 12 Func 1 - USB: EHCI */
+	Package(){0x0012FFFF, 0, 0, 18 },
+	Package(){0x0012FFFF, 1, 0, 17 },
+
+	/* Bus 0, Dev 13 Func 0 - USB: OHCI */
+	/* Bus 0, Dev 13 Func 1 - USB: EHCI */
+	Package(){0x0013FFFF, 0, 0, 18 },
+	Package(){0x0013FFFF, 1, 0, 17 },
+
+	/* Bus 0, Dev 10, Func 0 - USB: XHCI */
+	Package(){0x0010FFFF, 0, 0, 18 },
+
+	/* Bus 0, Dev 11 - SATA controller */
+	Package(){0x0011FFFF, 0, 0, 19 },
+})
+
+/* GPP 0 - PCIe 4x slot */
+Name(PS4, Package(){
+	Package(){0x0000FFFF, 0, INTA, 0 },
+	Package(){0x0000FFFF, 1, INTB, 0 },
+	Package(){0x0000FFFF, 2, INTC, 0 },
+	Package(){0x0000FFFF, 3, INTD, 0 },
+})
+Name(APS4, Package(){
+	Package(){0x0000FFFF, 0, 0, 16 },
+	Package(){0x0000FFFF, 1, 0, 17 },
+	Package(){0x0000FFFF, 2, 0, 18 },
+	Package(){0x0000FFFF, 3, 0, 19 },
+})
+
+/* GPP 1 - not used */
+Name(PS5, Package(){
+	Package(){0x0000FFFF, 0, INTB, 0 },
+	Package(){0x0000FFFF, 1, INTC, 0 },
+	Package(){0x0000FFFF, 2, INTD, 0 },
+	Package(){0x0000FFFF, 3, INTA, 0 },
+})
+Name(APS5, Package(){
+	Package(){0x0000FFFF, 0, 0, 28 },
+	Package(){0x0000FFFF, 1, 0, 29 },
+	Package(){0x0000FFFF, 2, 0, 30 },
+	Package(){0x0000FFFF, 3, 0, 31 },
+})
+
+/* GPP 2 - not used */
+Name(PS6, Package(){
+	Package(){0x0000FFFF, 0, INTC, 0 },
+	Package(){0x0000FFFF, 1, INTD, 0 },
+	Package(){0x0000FFFF, 2, INTA, 0 },
+	Package(){0x0000FFFF, 3, INTB, 0 },
+})
+Name(APS6, Package(){
+	Package(){0x0000FFFF, 0, 0, 32 },
+	Package(){0x0000FFFF, 1, 0, 33 },
+	Package(){0x0000FFFF, 2, 0, 34 },
+	Package(){0x0000FFFF, 3, 0, 35 },
+})
+
+/* GPP 3 - not used */
+Name(PS7, Package(){
+	Package(){0x0000FFFF, 0, INTD, 0 },
+	Package(){0x0000FFFF, 1, INTA, 0 },
+	Package(){0x0000FFFF, 2, INTB, 0 },
+	Package(){0x0000FFFF, 3, INTC, 0 },
+})
+Name(APS7, Package(){
+	Package(){0x0000FFFF, 0, 0, 36 },
+	Package(){0x0000FFFF, 1, 0, 37 },
+	Package(){0x0000FFFF, 2, 0, 38 },
+	Package(){0x0000FFFF, 3, 0, 39 },
+})
+
+/* GPP 4 - Realtek GBE */
+Name(PS8, Package(){
+	Package(){0x0000FFFF, 0, INTB, 0 },
+	Package(){0x0000FFFF, 1, INTC, 0 },
+	Package(){0x0000FFFF, 2, INTD, 0 },
+	Package(){0x0000FFFF, 3, INTA, 0 },
+})
+Name(APS8, Package(){
+	Package(){0x0000FFFF, 0, 0, 17 },
+	Package(){0x0000FFFF, 1, 0, 18 },
+	Package(){0x0000FFFF, 2, 0, 19 },
+	Package(){0x0000FFFF, 3, 0, 16 },
+})
diff --git a/src/mainboard/asus/am1i-a/acpi/sata.asl b/src/mainboard/asus/am1i-a/acpi/sata.asl
new file mode 100644
index 0000000000..9349be71e6
--- /dev/null
+++ b/src/mainboard/asus/am1i-a/acpi/sata.asl
@@ -0,0 +1,131 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012-2013 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+Name(STTM, Buffer(20) {
+	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
+	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
+	0x1f, 0x00, 0x00, 0x00
+})
+
+/* Start by clearing the PhyRdyChg bits */
+Method(_INI) {
+	\_GPE._L1F()
+}
+
+Device(PMRY)
+{
+	Name(_ADR, 0)
+	Method(_GTM, 0x0, NotSerialized) {
+		Return(STTM)
+	}
+	Method(_STM, 0x3, NotSerialized) {}
+
+	Device(PMST) {
+		Name(_ADR, 0)
+		Method(_STA,0) {
+			if (LGreater(P0IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return  (0x00) /* sata is missing */
+			}
+		}
+	}/* end of PMST */
+
+	Device(PSLA)
+	{
+		Name(_ADR, 1)
+		Method(_STA,0) {
+			if (LGreater(P1IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return (0x00) /* sata is missing */
+			}
+		}
+	}	/* end of PSLA */
+}   /* end of PMRY */
+
+Device(SEDY)
+{
+	Name(_ADR, 1)		/* IDE Scondary Channel */
+	Method(_GTM, 0x0, NotSerialized) {
+		Return(STTM)
+	}
+	Method(_STM, 0x3, NotSerialized) {}
+
+	Device(SMST)
+	{
+		Name(_ADR, 0)
+		Method(_STA,0) {
+			if (LGreater(P2IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return (0x00) /* sata is missing */
+			}
+		}
+	} /* end of SMST */
+
+	Device(SSLA)
+	{
+		Name(_ADR, 1)
+		Method(_STA,0) {
+			if (LGreater(P3IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return (0x00) /* sata is missing */
+			}
+		}
+	} /* end of SSLA */
+}   /* end of SEDY */
+
+/* SATA Hot Plug Support */
+Scope(\_GPE) {
+	Method(_L1F,0x0,NotSerialized) {
+		if (\_SB.P0PR) {
+			if (LGreater(\_SB.P0IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P0PR)
+		}
+
+		if (\_SB.P1PR) {
+			if (LGreater(\_SB.P1IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P1PR)
+		}
+
+		if (\_SB.P2PR) {
+			if (LGreater(\_SB.P2IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P2PR)
+		}
+
+		if (\_SB.P3PR) {
+			if (LGreater(\_SB.P3IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P3PR)
+		}
+	}
+}
diff --git a/src/mainboard/asus/am1i-a/acpi/si.asl b/src/mainboard/asus/am1i-a/acpi/si.asl
new file mode 100644
index 0000000000..292347127e
--- /dev/null
+++ b/src/mainboard/asus/am1i-a/acpi/si.asl
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+Scope(\_SI) {
+	Method(_SST, 1) {
+		/* DBGO("\\_SI\\_SST\n") */
+		/* DBGO("   New Indicator state: ") */
+		/* DBGO(Arg0) */
+		/* DBGO("\n") */
+	}
+} /* End Scope SI */
diff --git a/src/mainboard/asus/am1i-a/acpi/sleep.asl b/src/mainboard/asus/am1i-a/acpi/sleep.asl
new file mode 100644
index 0000000000..1225a62785
--- /dev/null
+++ b/src/mainboard/asus/am1i-a/acpi/sleep.asl
@@ -0,0 +1,93 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* Wake status package */
+Name(WKST,Package(){Zero, Zero})
+
+/*
+* \_PTS - Prepare to Sleep method
+*
+*	Entry:
+*		Arg0=The value of the sleeping state S1=1, S2=2, etc
+*
+* Exit:
+*		-none-
+*
+* The _PTS control method is executed at the beginning of the sleep process
+* for S1-S5. The sleeping value is passed to the _PTS control method.  This
+* control method may be executed a relatively long time before entering the
+* sleep state and the OS may abort the operation without notification to
+* the ACPI driver.  This method cannot modify the configuration or power
+* state of any device in the system.
+*/
+
+External(\_SB.APTS, MethodObj)
+External(\_SB.AWAK, MethodObj)
+
+Method(_PTS, 1) {
+	/* DBGO("\\_PTS\n") */
+	/* DBGO("From S0 to S") */
+	/* DBGO(Arg0) */
+	/* DBGO("\n") */
+
+	/* Clear wake status structure. */
+	Store(0, Index(WKST,0))
+	Store(0, Index(WKST,1))
+	Store(7, UPWS)
+	\_SB.APTS(Arg0)
+} /* End Method(\_PTS) */
+
+/*
+*	\_BFS OEM Back From Sleep method
+*
+*	Entry:
+*		Arg0=The value of the sleeping state S1=1, S2=2
+*
+*	Exit:
+*		-none-
+*/
+Method(\_BFS, 1) {
+	/* DBGO("\\_BFS\n") */
+	/* DBGO("From S") */
+	/* DBGO(Arg0) */
+	/* DBGO(" to S0\n") */
+}
+
+/*
+*  \_WAK System Wake method
+*
+*	Entry:
+*		Arg0=The value of the sleeping state S1=1, S2=2
+*
+*	Exit:
+*		Return package of 2 DWords
+*		Dword 1 - Status
+*			0x00000000	wake succeeded
+*			0x00000001	Wake was signaled but failed due to lack of power
+*			0x00000002	Wake was signaled but failed due to thermal condition
+*		Dword 2 - Power Supply state
+*			if non-zero the effective S-state the power supply entered
+*/
+Method(\_WAK, 1) {
+	/* DBGO("\\_WAK\n") */
+	/* DBGO("From S") */
+	/* DBGO(Arg0) */
+	/* DBGO(" to S0\n") */
+	Store(1,USBS)
+
+	\_SB.AWAK(Arg0)
+
+	Return(WKST)
+} /* End Method(\_WAK) */
diff --git a/src/mainboard/asus/am1i-a/acpi/superio.asl b/src/mainboard/asus/am1i-a/acpi/superio.asl
new file mode 100644
index 0000000000..6ff5b7fc09
--- /dev/null
+++ b/src/mainboard/asus/am1i-a/acpi/superio.asl
@@ -0,0 +1,111 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ * Copyright (C) 2015 Sergej Ivanov <getinaks@gmail.com>
+ * Copyright (C) 2018 Gergely Kiss <mail.gery@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+// Scope is \_SB.PCI0.LPCB
+
+// Values, defined here, must match settings in devicetree.cb
+
+Device (PS2M) {
+	Name (_HID, EisaId ("PNP0F13"))
+	Name (_CRS, ResourceTemplate () {
+		IRQNoFlags () {12}
+	})
+}
+
+Device (PS2K) {
+	Name (_HID, EisaId ("PNP0303"))
+	Name (_CRS, ResourceTemplate () {
+		IO (Decode16, 0x0060, 0x0060, 0x00, 0x01)
+		IO (Decode16, 0x0064, 0x0064, 0x00, 0x01)
+		IRQNoFlags () {1}
+	})
+}
+
+Device (COM1) {
+	Name (_HID, EISAID ("PNP0501"))
+	Name (_UID, 1)
+	Name (_CRS, ResourceTemplate ()
+	{
+		IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08)
+		IRQNoFlags () {4}
+	})
+	Name (_PRS, ResourceTemplate ()
+	{
+		IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08)
+		IRQNoFlags () {4}
+	})
+}
+
+Device (COM2) {
+	Name (_HID, EISAID ("PNP0501"))
+	Name (_UID, 2)
+	Name (_CRS, ResourceTemplate ()
+	{
+		IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08)
+		IRQNoFlags () {3}
+	})
+	Name (_PRS, ResourceTemplate ()
+	{
+		IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08)
+		IRQNoFlags () {3}
+	})
+}
+
+Device (LPT1) {
+	Name (_HID, EISAID ("PNP0401"))
+	Name (_UID, 1)
+	Name (_CRS, ResourceTemplate ()
+	{
+		IO (Decode16, 0x0378, 0x0378, 0x04, 0x08)
+		IO (Decode16, 0x0778, 0x0778, 0x04, 0x08)
+		IRQNoFlags () {5}
+	})
+	Name (_PRS, ResourceTemplate ()
+	{
+		IO (Decode16, 0x0378, 0x0378, 0x04, 0x08)
+		IO (Decode16, 0x0778, 0x0778, 0x04, 0x08)
+		IRQNoFlags () {5}
+	})
+}
+
+Device (ENVC) {
+	Name (_HID, EISAID ("PNP0C02"))
+	Name (_UID, 1)
+	Name (_CRS, ResourceTemplate ()
+	{
+		IO (Decode16, 0x0230, 0x0230, 0x04, 0x10)
+		IO (Decode16, 0x0290, 0x0290, 0x04, 0x10)
+	})
+	Name (_PRS, ResourceTemplate ()
+	{
+		IO (Decode16, 0x0230, 0x0230, 0x04, 0x10)
+		IO (Decode16, 0x0290, 0x0290, 0x04, 0x10)
+	})
+}
+
+Device (GPIC) {
+	Name (_HID, EISAID ("PNP0C02"))
+	Name (_UID, 2)
+	Name (_CRS, ResourceTemplate ()
+	{
+		IO (Decode16, 0x0300, 0x0300, 0x04, 0x20)
+	})
+	Name (_PRS, ResourceTemplate ()
+	{
+		IO (Decode16, 0x0300, 0x0300, 0x04, 0x20)
+	})
+}