Remove all AMD K8 boards

Platforms with LATE_CBMEM_INIT were agreed to be
removed with 4.7 release late 2017.

Change-Id: I0ecbb40f8c7ebdf68217f50af5624905d9005c64
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

9 files changed, 0 insertions, 842 deletions

diff --git a/src/mainboard/asus/a8v-e_se/Kconfig b/src/mainboard/asus/a8v-e_se/Kconfig
deleted file mode 100644
index 0188ff98b5..0000000000
--- a/src/mainboard/asus/a8v-e_se/Kconfig
+++ /dev/null
@@ -1,60 +0,0 @@
-if BOARD_ASUS_A8V_E_SE
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-	select CPU_AMD_SOCKET_939
-	select K8_HT_FREQ_1G_SUPPORT
-	select NORTHBRIDGE_AMD_AMDK8
-	select SOUTHBRIDGE_VIA_VT8237R
-	select SOUTHBRIDGE_VIA_K8T890
-	select SOUTHBRIDGE_VIA_SUBTYPE_K8T890
-	select SUPERIO_WINBOND_W83627EHG
-	select HAVE_OPTION_TABLE
-	select HAVE_ACPI_TABLES
-	select HAVE_MP_TABLE
-	select BOARD_ROMSIZE_KB_512
-	select RAMINIT_SYSINFO
-	select QRANK_DIMM_SUPPORT
-	select SET_FIDVID
-
-config MAINBOARD_DIR
-	string
-	default asus/a8v-e_se
-
-config DCACHE_RAM_BASE
-	hex
-	default 0xcc000
-
-config DCACHE_RAM_SIZE
-	hex
-	default 0x4000
-
-config APIC_ID_OFFSET
-	hex
-	default 0x10
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "A8V-E SE"
-
-config HW_MEM_HOLE_SIZEK
-	hex
-	default 0x0
-
-config MAX_CPUS
-	int
-	default 2
-
-config MAX_PHYSICAL_CPUS
-	int
-	default 1
-
-config HT_CHAIN_END_UNITID_BASE
-	hex
-	default 0x20
-
-config HT_CHAIN_UNITID_BASE
-	hex
-	default 0x0
-
-endif # BOARD_ASUS_A8V_E_SE
diff --git a/src/mainboard/asus/a8v-e_se/Kconfig.name b/src/mainboard/asus/a8v-e_se/Kconfig.name
deleted file mode 100644
index 34afcd89c0..0000000000
--- a/src/mainboard/asus/a8v-e_se/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_ASUS_A8V_E_SE
-	bool "A8V-E SE"
diff --git a/src/mainboard/asus/a8v-e_se/acpi_tables.c b/src/mainboard/asus/a8v-e_se/acpi_tables.c
deleted file mode 100644
index ab9811a127..0000000000
--- a/src/mainboard/asus/a8v-e_se/acpi_tables.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Written by Stefan Reinauer <stepan@openbios.org>.
- * ACPI FADT, FACS, and DSDT table support added by
- *
- * Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org>
- * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com>
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <device/device.h>
-#include <device/pci_ids.h>
-#include "southbridge/via/vt8237r/vt8237r.h"
-#include "southbridge/via/k8t890/k8t890.h"
-#include "northbridge/amd/amdk8/acpi.h"
-#include <cpu/amd/powernow.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-void get_bus_conf(void)
-{
-	/* FIXME: implement this.  */
-}
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
-	unsigned int gsi_base = 0x18;
-
-	/* Create all subtables for processors. */
-	current = acpi_create_madt_lapics(current);
-
-	/* Write SB IOAPIC. */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
-				VT8237R_APIC_ID, IO_APIC_ADDR, 0);
-
-	/* Write NB IOAPIC. */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
-				K8T890_APIC_ID, K8T890_APIC_BASE, gsi_base);
-
-	/* IRQ9 ACPI active low. */
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-		current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
-
-	/* IRQ0 -> APIC IRQ2. */
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-						current, 0, 0, 2, 0x0);
-
-	/* Create all subtables for processors. */
-	current = acpi_create_madt_lapic_nmis(current,
-			MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
-
-	return current;
-}
diff --git a/src/mainboard/asus/a8v-e_se/board_info.txt b/src/mainboard/asus/a8v-e_se/board_info.txt
deleted file mode 100644
index c08475a48b..0000000000
--- a/src/mainboard/asus/a8v-e_se/board_info.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Category: desktop
-Board URL: http://www.asus.com/Motherboards/AMD_Socket_939/A8VE_SE/
-ROM package: PLCC
-ROM protocol: LPC
-ROM socketed: y
-Flashrom support: y
-Release year: 2006
diff --git a/src/mainboard/asus/a8v-e_se/cmos.layout b/src/mainboard/asus/a8v-e_se/cmos.layout
deleted file mode 100644
index aae7ceb075..0000000000
--- a/src/mainboard/asus/a8v-e_se/cmos.layout
+++ /dev/null
@@ -1,52 +0,0 @@
-entries
-
-0          384       r       0        reserved_memory
-384          1       e       4        boot_option
-388          4       h       0        reboot_counter
-#392          3       r       0        unused
-395          1       e       1        hw_scrubber
-396          1       e       1        interleave_chip_selects
-397          2       e       8        max_mem_clock
-399         1       e       2        multi_core
-400          1       e       1        power_on_after_fail
-412          4       e       6        debug_level
-440          4       e       9        slow_cpu
-444          1       e       1        nmi
-445          1       e       1        iommu
-456          1       e       1        ECC_memory
-728        256       h       0        user_data
-984         16       h       0        check_sum
-# Reserve the extended AMD configuration registers
-1000        24       r       0        amd_reserved
-
-
-
-enumerations
-
-#ID value   text
-1     0     Disable
-1     1     Enable
-2     0     Enable
-2     1     Disable
-4     0     Fallback
-4     1     Normal
-6     5     Notice
-6     6     Info
-6     7     Debug
-6     8     Spew
-8     0     DDR400
-8     1     DDR333
-8     2     DDR266
-8     3     DDR200
-9     0     off
-9     1     87.5%
-9     2     75.0%
-9     3     62.5%
-9     4     50.0%
-9     5     37.5%
-9     6     25.0%
-9     7     12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/asus/a8v-e_se/devicetree.cb b/src/mainboard/asus/a8v-e_se/devicetree.cb
deleted file mode 100644
index f2d078a74e..0000000000
--- a/src/mainboard/asus/a8v-e_se/devicetree.cb
+++ /dev/null
@@ -1,97 +0,0 @@
-chip northbridge/amd/amdk8/root_complex		# Root complex
-  device cpu_cluster 0 on			# APIC cluster
-    chip cpu/amd/socket_939			# CPU
-      device lapic 0 on end			# APIC
-    end
-  end
-  device domain 0 on			# PCI domain
-    subsystemid 0x1043 0 inherit
-    chip northbridge/amd/amdk8			# mc0
-      device pci 18.0 on			# Northbridge
-        # Devices on link 0, link 0 == LDT 0
-        chip southbridge/via/vt8237r		# Southbridge
-          register "ide0_enable" = "1"		# Enable IDE channel 0
-          register "ide1_enable" = "1"		# Enable IDE channel 1
-          register "ide0_80pin_cable" = "1"	# 80pin cable on IDE channel 0
-          register "ide1_80pin_cable" = "1"	# 80pin cable on IDE channel 1
-          register "fn_ctrl_lo" = "0"		# Enable SB functions
-          register "fn_ctrl_hi" = "0xad"	# Enable SB functions
-          device pci 0.0 on end			# HT
-          device pci f.1 on end			# IDE
-          device pci 11.0 on			# LPC
-            chip drivers/generic/generic	# DIMM 0-0-0
-              device i2c 50 on end
-            end
-            chip drivers/generic/generic	# DIMM 0-0-1
-              device i2c 51 on end
-            end
-            chip drivers/generic/generic	# DIMM 0-1-0
-              device i2c 52 on end
-            end
-            chip drivers/generic/generic	# DIMM 0-1-1
-              device i2c 53 on end
-            end
-            chip superio/winbond/w83627ehg	# Super I/O
-              device pnp 2e.0 on		# Floppy
-                io 0x60 = 0x3f0
-                irq 0x70 = 6
-                drq 0x74 = 2
-              end
-              device pnp 2e.1 on		# Parallel port
-                io 0x60 = 0x378
-                irq 0x70 = 7
-                drq 0x74 = 3
-              end
-              device pnp 2e.2 on		# Com1
-                io 0x60 = 0x3f8
-                irq 0x70 = 4
-              end
-              device pnp 2e.3 off		# Com2 (N/A on this board)
-                io 0x60 = 0x2f8
-                irq 0x70 = 3
-              end
-              device pnp 2e.5 off		# PS/2 keyboard & mouse (off)
-              end
-              device pnp 2e.106 off		# Serial flash interface (SFI)
-                io 0x60 = 0x100
-              end
-              device pnp 2e.007 off		# GPIO 1
-              end
-              device pnp 2e.107 on		# Game port
-                io 0x60 = 0x201
-              end
-              device pnp 2e.207 on		# MIDI
-                io 0x62 = 0x330
-                irq 0x70 = 0xa
-              end
-              device pnp 2e.307 off		# GPIO 6
-              end
-              device pnp 2e.8 off		# WDTO#, PLED
-              end
-              device pnp 2e.009 on		# GPIO 2
-              end
-              device pnp 2e.109 off		# GPIO 3
-              end
-              device pnp 2e.209 off		# GPIO 4
-              end
-              device pnp 2e.309 on		# GPIO 5
-              end
-              device pnp 2e.a off		# ACPI
-              end
-              device pnp 2e.b on		# Hardware monitor
-                io 0x60 = 0x290
-                irq 0x70 = 0
-              end
-            end
-          end
-          device pci 12.0 off end		# VIA LAN (off, other chip used)
-        end
-        chip southbridge/via/k8t890		# "Southbridge" K8T890
-        end
-      end
-      device pci 18.1 on end
-      device pci 18.2 on end
-      device pci 18.3 on end
-    end
-  end
-end
diff --git a/src/mainboard/asus/a8v-e_se/dsdt.asl b/src/mainboard/asus/a8v-e_se/dsdt.asl
deleted file mode 100644
index 1da24173e3..0000000000
--- a/src/mainboard/asus/a8v-e_se/dsdt.asl
+++ /dev/null
@@ -1,239 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/*
- * ISA portions taken from QEMU acpi-dsdt.dsl.
- */
-
-DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE  ", "COREBOOT", 1)
-{
-	 #include "northbridge/amd/amdk8/util.asl"
-
-	#include <southbridge/via/k8t890/acpi/sleepstates.asl>
-
-	/* Root of the bus hierarchy */
-	Scope (\_SB)
-	{
-		/* Top PCI device */
-		Device (PCI0)
-		{
-			Name (_HID, EisaId ("PNP0A03"))
-			Name (_ADR, 0x00)
-			Name (_UID, 0x00)
-			Name (_BBN, 0x00)
-
-		    External (BUSN)
-		    External (MMIO)
-		    External (PCIO)
-		    External (SBLK)
-		    External (TOM1)
-		    External (HCLK)
-		    External (SBDN)
-		    External (HCDN)
-
-		    Method (_CRS, 0, NotSerialized)
-			{
-			    Name (BUF0, ResourceTemplate ()
-			    {
-				IO (Decode16,
-				0x0CF8,             // Address Range Minimum
-				0x0CF8,             // Address Range Maximum
-				0x01,               // Address Alignment
-				0x08,               // Address Length
-				)
-				WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-				0x0000,             // Address Space Granularity
-				0x0000,             // Address Range Minimum
-				0x0CF7,             // Address Range Maximum
-				0x0000,             // Address Translation Offset
-				0x0CF8,             // Address Length
-				,, , TypeStatic)
-			    })
-				/* Methods bellow use SSDT to get actual MMIO regs
-				   The IO ports are from 0xd00, optionally an VGA,
-				   otherwise the info from MMIO is used.
-				 */
-				Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
-				Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
-				Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
-				Return (Local3)
-			}
-
-			/* PCI Routing Table */
-			Name (_PRT, Package () {
-				Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */
-				Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 },
-				Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 },
-				Package (0x04) { 0x000BFFFF, 0x03, 0x00, 0x13 },
-				Package (0x04) { 0x000CFFFF, 0x00, 0x00, 0x11 }, /* Slot 0xC */
-				Package (0x04) { 0x000CFFFF, 0x01, 0x00, 0x12 },
-				Package (0x04) { 0x000CFFFF, 0x02, 0x00, 0x13 },
-				Package (0x04) { 0x000CFFFF, 0x03, 0x00, 0x10 },
-				Package (0x04) { 0x000DFFFF, 0x00, 0x00, 0x12 }, /* Slot 0xD */
-				Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 },
-				Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 },
-				Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 },
-				Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */
-				Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */
-				Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */
-				Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 },
-				Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 },
-				Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 },
-				Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, /* AC97, MC97 */
-				Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */
-				Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B },
-				Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B },
-				Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B },
-				Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */
-				Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */
-				Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */
-				Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B }  /* IRQ43 */
-			})
-
-			Device (PEGG)
-			{
-				Name (_ADR, 0x00020000)
-				Name (_UID, 0x00)
-				Name (_BBN, 0x02)
-				Name (_PRT, Package () {
-					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */
-					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 },
-					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A },
-					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B },
-				})
-			}
-
-			Device (PEX0)
-			{
-				Name (_ADR, 0x00030000)
-				Name (_UID, 0x00)
-				Name (_BBN, 0x03)
-				Name (_PRT, Package () {
-					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */
-					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D },
-					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E },
-					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F },
-				})
-			}
-
-			Device (PEX1)
-			{
-				Name (_ADR, 0x00030001)
-				Name (_UID, 0x00)
-				Name (_BBN, 0x04)
-				Name (_PRT, Package () {
-					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */
-					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 },
-					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 },
-					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 },
-				})
-			}
-
-			Device (PEX2)
-			{
-				Name (_ADR, 0x00030002)
-				Name (_UID, 0x00)
-				Name (_BBN, 0x05)
-				Name (_PRT, Package () {
-					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */
-					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 },
-					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 },
-					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 },
-				})
-			}
-
-			Device (PEX3)
-			{
-				Name (_ADR, 0x00030003)
-				Name (_UID, 0x00)
-				Name (_BBN, 0x06)
-				Name (_PRT, Package () {
-					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, /* PCIE IRQ40-IRQ43 */
-					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 },
-					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A },
-					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B },
-				})
-			}
-
-			Device (ISA) {
-				Name (_ADR, 0x00110000)
-
-				/* PS/2 keyboard (seems to be important for WinXP install) */
-				Device (KBD)
-				{
-					Name (_HID, EisaId ("PNP0303"))
-					Method (_STA, 0, NotSerialized)
-					{
-						Return (0x0f)
-					}
-					Method (_CRS, 0, NotSerialized)
-					{
-						Name (TMP, ResourceTemplate () {
-							IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
-							IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
-							IRQNoFlags () {1}
-						})
-						Return (TMP)
-					}
-				}
-
-				/* PS/2 mouse */
-				Device (MOU)
-				{
-					Name (_HID, EisaId ("PNP0F13"))
-					Method (_STA, 0, NotSerialized)
-					{
-						Return (0x0f)
-					}
-					Method (_CRS, 0, NotSerialized)
-					{
-						Name (TMP, ResourceTemplate () {
-						     IRQNoFlags () {12}
-						})
-						Return (TMP)
-					}
-				}
-
-				/* PS/2 floppy controller */
-				Device (FDC0)
-				{
-					Name (_HID, EisaId ("PNP0700"))
-					Method (_STA, 0, NotSerialized)
-					{
-						Return (0x0f)
-					}
-					Method (_CRS, 0, NotSerialized)
-					{
-						Name (BUF0, ResourceTemplate () {
-							IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04)
-							IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01)
-							IRQNoFlags () {6}
-							DMA (Compatibility, NotBusMaster, Transfer8) {2}
-						})
-						Return (BUF0)
-					}
-				}
-			}
-			/* Dummy device to hold auto generated reserved resources */
-			Device(MBRS) {
-				Name (_HID, EisaId ("PNP0C02"))
-				Name (_UID, 0x01)
-				External(_CRS) /* Resource Template in SSDT */
-			}
-
-		}
-	}
-}
diff --git a/src/mainboard/asus/a8v-e_se/mptable.c b/src/mainboard/asus/a8v-e_se/mptable.c
deleted file mode 100644
index f3d3d06207..0000000000
--- a/src/mainboard/asus/a8v-e_se/mptable.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <string.h>
-#include <stdint.h>
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include "southbridge/via/vt8237r/vt8237r.h"
-#include "southbridge/via/k8t890/k8t890.h"
-
-static void *smp_write_config_table(void *v)
-{
-	struct mp_config_table *mc;
-	int bus_isa;
-
-	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
-	mptable_init(mc, LOCAL_APIC_ADDR);
-
-	smp_write_processors(mc);
-
-	mptable_write_buses(mc, NULL, &bus_isa);
-
-	/* I/O APICs:	APIC ID	Version	State		Address */
-	smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, VIO_APIC_VADDR);
-	smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, (void *)K8T890_APIC_BASE);
-
-	mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0);
-
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xb << 2) | 0, VT8237R_APIC_ID, 0x10); //IRQ16
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xb << 2) | 1, VT8237R_APIC_ID, 0x11); //IRQ17
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xb << 2) | 2, VT8237R_APIC_ID, 0x12); //IRQ18
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xb << 2) | 3, VT8237R_APIC_ID, 0x13); //IRQ19
-
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xc << 2) | 0, VT8237R_APIC_ID, 0x11); //IRQ17
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xc << 2) | 1, VT8237R_APIC_ID, 0x12); //IRQ18
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xc << 2) | 2, VT8237R_APIC_ID, 0x13); //IRQ19
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xc << 2) | 3, VT8237R_APIC_ID, 0x10); //IRQ16
-
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xd << 2) | 0, VT8237R_APIC_ID, 0x12); //IRQ18
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xd << 2) | 1, VT8237R_APIC_ID, 0x13); //IRQ19
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xd << 2) | 2, VT8237R_APIC_ID, 0x10); //IRQ16
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xd << 2) | 3, VT8237R_APIC_ID, 0x11); //IRQ17
-
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xf << 2) | 0, VT8237R_APIC_ID, 0x14);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0xf << 2) | 1, VT8237R_APIC_ID, 0x14);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x10 << 2) | 0, VT8237R_APIC_ID, 0x15);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x10 << 2) | 1, VT8237R_APIC_ID, 0x15);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x10 << 2) | 2, VT8237R_APIC_ID, 0x15);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x11 << 2) | 2, VT8237R_APIC_ID, 0x16);
-
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x2 << 2) | 0, K8T890_APIC_ID, 0x3);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x2 << 2) | 1, K8T890_APIC_ID, 0x3);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x2 << 2) | 2, K8T890_APIC_ID, 0x3);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x2 << 2) | 3, K8T890_APIC_ID, 0x3);
-
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x3 << 2) | 0, K8T890_APIC_ID, 0x7);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x3 << 2) | 1, K8T890_APIC_ID, 0xb);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x3 << 2) | 2, K8T890_APIC_ID, 0xf);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x3 << 2) | 3, K8T890_APIC_ID, 0x13);
-
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2,  (0x00 << 2) | 0, K8T890_APIC_ID, 0x0);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2,  (0x00 << 2) | 1, K8T890_APIC_ID, 0x1);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2,  (0x00 << 2) | 2, K8T890_APIC_ID, 0x2);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2,  (0x00 << 2) | 3, K8T890_APIC_ID, 0x3);
-
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3,  (0x00 << 2) | 0, K8T890_APIC_ID, 0x4);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3,  (0x00 << 2) | 1, K8T890_APIC_ID, 0x5);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3,  (0x00 << 2) | 2, K8T890_APIC_ID, 0x6);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3,  (0x00 << 2) | 3, K8T890_APIC_ID, 0x7);
-
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4,  (0x00 << 2) | 0, K8T890_APIC_ID, 0x8);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4,  (0x00 << 2) | 1, K8T890_APIC_ID, 0x9);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4,  (0x00 << 2) | 2, K8T890_APIC_ID, 0xa);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4,  (0x00 << 2) | 3, K8T890_APIC_ID, 0xb);
-
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5,  (0x00 << 2) | 0, K8T890_APIC_ID, 0xc);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5,  (0x00 << 2) | 1, K8T890_APIC_ID, 0xd);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5,  (0x00 << 2) | 2, K8T890_APIC_ID, 0xe);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5,  (0x00 << 2) | 3, K8T890_APIC_ID, 0xf);
-
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6,  (0x00 << 2) | 0, K8T890_APIC_ID, 0x10);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6,  (0x00 << 2) | 1, K8T890_APIC_ID, 0x11);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6,  (0x00 << 2) | 2, K8T890_APIC_ID, 0x12);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6,  (0x00 << 2) | 3, K8T890_APIC_ID, 0x13);
-
-	/* Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN# */
-	mptable_lintsrc(mc, bus_isa);
-	/* There is no extension information... */
-
-	/* Compute the checksums. */
-	return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
-	void *v;
-	v = smp_write_floating_table(addr, 0);
-	return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c
deleted file mode 100644
index 2df2a48815..0000000000
--- a/src/mainboard/asus/a8v-e_se/romstage.c
+++ /dev/null
@@ -1,206 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 AMD
- * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
- * Copyright (C) 2006 MSI
- * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI)
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-unsigned int get_sbdn(unsigned bus);
-
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include <halt.h>
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-#include <cpu/x86/lapic.h>
-#include "northbridge/amd/amdk8/early_ht.c"
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627ehg/w83627ehg.h>
-#include <southbridge/via/vt8237r/vt8237r.h>
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include <spd.h>
-#include <northbridge/amd/amdk8/pre_f.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
-#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V)
-#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI)
-
-void memreset(int controllers, const struct mem_controller *ctrl) { }
-void activate_spd_rom(const struct mem_controller *ctrl) { }
-
-int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#include <reset.h>
-void do_soft_reset(void)
-{
-	uint8_t tmp;
-
-	set_bios_reset();
-	printk(BIOS_DEBUG, "soft reset\n");
-
-	/* PCI reset */
-	tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
-	tmp |= 0x01;
-	pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
-
-	halt();
-}
-
-#include "southbridge/via/k8t890/early_car.c"
-#include <northbridge/amd/amdk8/amdk8.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "northbridge/amd/amdk8/raminit.c"
-#include "lib/generic_sdram.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "cpu/amd/model_fxx/fidvid.c"
-#include "northbridge/amd/amdk8/resourcemap.c"
-
-unsigned int get_sbdn(unsigned bus)
-{
-	pci_devfn_t dev;
-
-	dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
-					PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
-	return (dev >> 15) & 0x1f;
-}
-
-static void sio_init(void)
-{
-	u8 reg;
-
-	pnp_enter_conf_state(SERIAL_DEV);
-	/* We have 24MHz input. */
-	reg = pnp_read_config(SERIAL_DEV, 0x24);
-	pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40));
-	/* We have GPIO for KB/MS pin. */
-	reg = pnp_read_config(SERIAL_DEV, 0x2a);
-	pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1));
-	/* We have all RESTOUT and even some reserved bits, too. */
-	reg = pnp_read_config(SERIAL_DEV, 0x2c);
-	pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0));
-	pnp_exit_conf_state(SERIAL_DEV);
-
-	pnp_enter_conf_state(ACPI_DEV);
-	pnp_set_logical_device(ACPI_DEV);
-	/*
-	 * Set the delay rising time from PWROK_LP to PWROK_ST to
-	 * 300 - 600ms, and 0 to vice versa.
-	 */
-	reg = pnp_read_config(ACPI_DEV, 0xe6);
-	pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0));
-	/* 1 Use external suspend clock source 32.768KHz. Undocumented?? */
-	reg = pnp_read_config(ACPI_DEV, 0xe4);
-	pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10));
-	pnp_exit_conf_state(ACPI_DEV);
-
-	pnp_enter_conf_state(GPIO_DEV);
-	pnp_set_logical_device(GPIO_DEV);
-	/* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */
-	pnp_write_config(GPIO_DEV, 0x30, 0x09);	/* Enable GPIO 2 & GPIO 5. */
-	pnp_write_config(GPIO_DEV, 0xe2, 0x00);	/* No inversion */
-	pnp_write_config(GPIO_DEV, 0xe5, 0x00);	/* No inversion */
-	pnp_write_config(GPIO_DEV, 0xe3, 0x03);	/* 0000 0011, 0 = output 1 = input */
-	pnp_write_config(GPIO_DEV, 0xe0, 0xde);	/* 1101 1110, 0 = output 1 = input */
-	pnp_write_config(GPIO_DEV, 0xe1, 0x01);	/* Set output val. */
-	pnp_write_config(GPIO_DEV, 0xe4, 0xb4);	/* Set output val (1011 0100). */
-	pnp_exit_conf_state(GPIO_DEV);
-}
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-	static const uint16_t spd_addr[] = {
-		// Node 0
-		DIMM0, DIMM2, 0, 0,
-		0, 0, 0, 0,
-		// Node 1
-		DIMM1, DIMM3, 0, 0,
-		0, 0, 0, 0,
-	};
-	unsigned bsp_apicid = 0;
-	int needs_reset = 0;
-	struct sys_info *sysinfo = &sysinfo_car;
-
-	sio_init();
-	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-	console_init();
-	enable_rom_decode();
-
-	printk(BIOS_INFO, "now booting... fallback\n");
-
-	/* Is this a CPU only reset? Or is this a secondary CPU? */
-	if (!cpu_init_detectedx && boot_cpu()) {
-		/* Nothing special needs to be done to find bus 0. */
-		/* Allow the HT devices to be found. */
-		enumerate_ht_chain();
-	}
-
-	printk(BIOS_INFO, "now booting... real_main\n");
-
-	if (bist == 0)
-		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-
-	/* Halt if there was a built in self test failure. */
-	report_bist_failure(bist);
-
-	setup_default_resource_map();
-	setup_coherent_ht_domain();
-	wait_all_core0_started();
-
-	printk(BIOS_INFO, "now booting... Core0 started\n");
-
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
-	/* It is said that we should start core1 after all core0 launched. */
-	start_other_cores();
-	wait_all_other_cores_started(bsp_apicid);
-#endif
-	init_timer();
-	ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
-
-	needs_reset = optimize_link_coherent_ht();
-	needs_reset |= optimize_link_incoherent_ht(sysinfo);
-	needs_reset |= k8t890_early_setup_ht();
-
-	if (needs_reset) {
-		printk(BIOS_DEBUG, "ht reset -\n");
-		soft_reset();
-	}
-
-	/* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */
-	enable_fid_change();
-	init_fidvid_bsp(bsp_apicid);
-
-	/* Stop the APs so we can start them later in init. */
-	allow_all_aps_stop(bsp_apicid);
-
-	/* It's the time to set ctrl now. */
-	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-
-	enable_smbus();
-	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
-}