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authorBalazs Vinarz <vinibali1@gmail.com>2019-01-18 10:53:13 +0100
committerAngel Pons <th3fanbus@gmail.com>2020-08-13 17:34:04 +0000
commitffa710b9dd241cc7545858a2ac69f7cdb214cddf (patch)
tree270c3262c06d9bf4280f46081d343a8e14e548b4 /src/mainboard/asus/a88xm-e/bootblock.c
parent414d7e4642991696dc81fbcb7ac68fe75fa4bc12 (diff)
mb/asus: Add Asus A88XM-E FM2+ with documentation
The port is based on the F2A85-M, the main differences are: - 2 DDR3 dimms - 2 PS/2 ports - 2*USB2.0 and 2*USB3.0 ports - 3+2 phase VRM - 6 channel audio - 6 SATA ports - ASP1206 VRM controller - Bolton D4 chipset - no optical SPDIF/IO Successfully booted configurations: -RAM: 2*8GB Kingston KVR 1333Mhz LP, 2*8GB Crucial BLT8G3D1869DT1TX0 -CPU: AMD A8-6500 (Richland), AMD A10-6700 (Richland) -OS: Arch Linux 4.19 (SATA, USB), Linux Mint 19.3, Artix Linux 2019 -SeaBIOS: 1.12 and 1.13 Known problems: - IRQ routing is done incorrect way - common problem of fam15h boards - Windows 7 can't boot because of the incomplete ACPI implementation Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90 Signed-off-by: Balazs Vinarz <vinibali1@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30987 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/asus/a88xm-e/bootblock.c')
-rw-r--r--src/mainboard/asus/a88xm-e/bootblock.c38
1 files changed, 38 insertions, 0 deletions
diff --git a/src/mainboard/asus/a88xm-e/bootblock.c b/src/mainboard/asus/a88xm-e/bootblock.c
new file mode 100644
index 0000000000..0bc8d2e15e
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/bootblock.c
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/acpimmio.h>
+#include <bootblock_common.h>
+#include <device/pnp_type.h>
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8728f/it8728f.h>
+
+static void sbxxx_enable_48mhzout(void)
+{
+ /* Set auxiliary output clock frequency on OSCOUT2 pin to be 48MHz */
+ u32 reg32;
+ reg32 = misc_read32(0x28);
+ reg32 &= ~(7 << 19);
+ reg32 |= (2 << 19);
+ misc_write32(0x28, reg32);
+
+ /* Enable Auxiliary OSCOUT2 */
+ misc_write32(0x40, misc_read32(0x40) & ~(1 << 7));
+}
+
+static void superio_init_m(void)
+{
+ const pnp_devfn_t uart = PNP_DEV(0x2e, IT8728F_SP1);
+ const pnp_devfn_t gpio = PNP_DEV(0x2e, IT8728F_GPIO);
+
+ ite_kill_watchdog(gpio);
+ ite_enable_serial(uart, CONFIG_TTYS0_BASE);
+ ite_enable_3vsbsw(gpio);
+}
+
+void bootblock_mainboard_early_init(void)
+{
+ /* enable SIO clock */
+ sbxxx_enable_48mhzout();
+
+ superio_init_m();
+}