mb/asus: Add Asus A88XM-E FM2+ with documentation

The port is based on the F2A85-M, the main differences are:
- 2 DDR3 dimms
- 2 PS/2 ports
- 2*USB2.0 and 2*USB3.0 ports
- 3+2 phase VRM
- 6 channel audio
- 6 SATA ports
- ASP1206 VRM controller
- Bolton D4 chipset
- no optical SPDIF/IO

Successfully booted configurations:
-RAM: 2*8GB Kingston KVR 1333Mhz LP, 2*8GB Crucial BLT8G3D1869DT1TX0
-CPU: AMD A8-6500 (Richland), AMD A10-6700 (Richland)
-OS:  Arch Linux 4.19 (SATA, USB), Linux Mint 19.3, Artix Linux 2019
-SeaBIOS: 1.12 and 1.13

Known problems:
- IRQ routing is done incorrect way - common problem of fam15h boards
- Windows 7 can't boot because of the incomplete ACPI implementation

Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
Signed-off-by: Balazs Vinarz <vinibali1@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30987
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 83 insertions, 0 deletions

diff --git a/src/mainboard/asus/a88xm-e/acpi/cpstate.asl b/src/mainboard/asus/a88xm-e/acpi/cpstate.asl
new file mode 100644
index 0000000000..35583de49f
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/cpstate.asl
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file defines the processor and performance state capability
+ * for each core in the system.  It is included into the DSDT for each
+ * core.  It assumes that each core of the system has the same performance
+ * characteristics.
+ */
+
+/*
+ * P-state support: the maximum number of P-states supported
+ * by the CPUs that we'll use - is 6. Taken from AMI BIOS.
+ */
+Name(_PSS, Package(){
+	Package()
+	{
+		0x00000D48,
+		0x00011170,
+		0x00000004,
+		0x00000004,
+		0x00000000,
+		0x00000000
+	},
+
+	Package()
+	{
+		0x00000AF0,
+		0x0000C544,
+		0x00000004,
+		0x00000004,
+		0x00000001,
+		0x00000001
+	},
+
+	Package()
+	{
+		0x000009C4,
+		0x0000B3B0,
+		0x00000004,
+		0x00000004,
+		0x00000002,
+		0x00000002
+	},
+
+	Package()
+	{
+		0x00000898,
+		0x0000ABE0,
+		0x00000004,
+		0x00000004,
+		0x00000003,
+		0x00000003
+	},
+
+	Package()
+	{
+		0x00000708,
+		0x0000A410,
+		0x00000004,
+		0x00000004,
+		0x00000004,
+		0x00000004
+	},
+
+	Package()
+	{
+		0x00000578,
+		0x00006F54,
+		0x00000004,
+		0x00000004,
+		0x00000005,
+		0x00000005
+	}
+})
+
+Name(_PCT, Package(){
+	ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
+	ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
+})
+
+Method(_PPC, 0){
+	Return(0)
+}