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authorArthur Heymans <arthur@aheymans.xyz>2022-11-01 23:22:55 +0100
committerArthur Heymans <arthur@aheymans.xyz>2022-11-07 13:57:06 +0000
commitf9decbb0c720662d8e71fe221aef55b7ecf76196 (patch)
tree06b2198767b4c86b7d36e7ddd6a5f56b4a1fbc54 /src/mainboard/asrock
parente56f0c7cab77b89a750b4a3f7f380b1a10cd0d1d (diff)
mb/*/*: Remove AMD family14 boards
These boards use the LEGACY_SMP_INIT which is to be deprecated after release 4.18. Change-Id: I3495d140a244bbbf63e846fcd963d69907e09719 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/asrock')
-rw-r--r--src/mainboard/asrock/e350m1/BiosCallOuts.c97
-rw-r--r--src/mainboard/asrock/e350m1/Kconfig45
-rw-r--r--src/mainboard/asrock/e350m1/Kconfig.name2
-rw-r--r--src/mainboard/asrock/e350m1/Makefile.inc11
-rw-r--r--src/mainboard/asrock/e350m1/OemCustomize.c79
-rw-r--r--src/mainboard/asrock/e350m1/OptionsIds.h37
-rw-r--r--src/mainboard/asrock/e350m1/acpi/gpe.asl54
-rw-r--r--src/mainboard/asrock/e350m1/acpi/routing.asl382
-rw-r--r--src/mainboard/asrock/e350m1/acpi/sata.asl132
-rw-r--r--src/mainboard/asrock/e350m1/acpi/sleep.asl88
-rw-r--r--src/mainboard/asrock/e350m1/acpi/superio.asl3
-rw-r--r--src/mainboard/asrock/e350m1/acpi/usb_oc.asl148
-rw-r--r--src/mainboard/asrock/e350m1/board_info.txt7
-rw-r--r--src/mainboard/asrock/e350m1/bootblock.c12
-rw-r--r--src/mainboard/asrock/e350m1/buildOpts.c42
-rw-r--r--src/mainboard/asrock/e350m1/cmos.layout38
-rw-r--r--src/mainboard/asrock/e350m1/devicetree.cb130
-rw-r--r--src/mainboard/asrock/e350m1/dsdt.asl46
-rw-r--r--src/mainboard/asrock/e350m1/irq_tables.c88
-rw-r--r--src/mainboard/asrock/e350m1/mainboard.c56
-rw-r--r--src/mainboard/asrock/e350m1/platform_cfg.h202
21 files changed, 0 insertions, 1699 deletions
diff --git a/src/mainboard/asrock/e350m1/BiosCallOuts.c b/src/mainboard/asrock/e350m1/BiosCallOuts.c
deleted file mode 100644
index ac42bd4f45..0000000000
--- a/src/mainboard/asrock/e350m1/BiosCallOuts.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <AGESA.h>
-#include <amdlib.h>
-#include <amdblocks/acpimmio.h>
-#include <northbridge/amd/agesa/BiosCallOuts.h>
-#include <SB800.h>
-
-static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr);
-
-const BIOS_CALLOUT_STRUCT BiosCallouts[] =
-{
- {AGESA_DO_RESET, agesa_Reset },
- {AGESA_READ_SPD, agesa_ReadSpd },
- {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
- {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
- {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
- {AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit },
- {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
- {AGESA_GNB_PCIE_SLOT_RESET, agesa_NoopUnsupported },
-};
-const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
-
-/* Call the host environment interface to provide a user hook opportunity. */
-static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr)
-{
- AGESA_STATUS Status;
- MEM_DATA_STRUCT *MemData;
- UINT32 GpioMmioAddr;
- UINT8 Data8;
- UINT8 TempData8;
-
- MemData = ConfigPtr;
-
- Status = AGESA_SUCCESS;
- GpioMmioAddr = (uintptr_t)acpimmio_gpio_100;
-
- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
- Data8 &= ~BIT5;
- TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
- TempData8 &= 0x03;
- TempData8 |= Data8;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
-
- Data8 |= BIT2+BIT3;
- Data8 &= ~BIT4;
- TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
- TempData8 &= 0x23;
- TempData8 |= Data8;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
- Data8 &= ~BIT5;
- TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
- TempData8 &= 0x03;
- TempData8 |= Data8;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
- Data8 |= BIT2+BIT3;
- Data8 &= ~BIT4;
- TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
- TempData8 &= 0x23;
- TempData8 |= Data8;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
-
- /*
- * this seems to be just copy-pasted from the AMD reference boards and
- * needs some investigation
- */
- switch (MemData->ParameterListPtr->DDR3Voltage) {
- case VOLT1_35:
- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
- Data8 &= ~(UINT8)BIT6;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
- Data8 |= (UINT8)BIT6;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
- break;
- case VOLT1_25:
- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
- Data8 &= ~(UINT8)BIT6;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
- Data8 &= ~(UINT8)BIT6;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
- break;
- case VOLT1_5:
- default:
- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
- Data8 |= (UINT8)BIT6;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
- Data8 &= ~(UINT8)BIT6;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
- }
- /* disable memory clear for boot time reduction */
- MemData->ParameterListPtr->EnableMemClr = FALSE;
- return Status;
-}
diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig
deleted file mode 100644
index 90b457d5e2..0000000000
--- a/src/mainboard/asrock/e350m1/Kconfig
+++ /dev/null
@@ -1,45 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-if BOARD_ASROCK_E350M1
-
-config BOARD_SPECIFIC_OPTIONS
- def_bool y
- select CPU_AMD_AGESA_FAMILY14
- select NORTHBRIDGE_AMD_AGESA_FAMILY14
- select SOUTHBRIDGE_AMD_CIMX_SB800
- select SUPERIO_NUVOTON_NCT5572D
- select SB_SUPERIO_HWM
- select HAVE_OPTION_TABLE
- select HAVE_PIRQ_TABLE
- select HAVE_ACPI_RESUME
- select HAVE_ACPI_TABLES
- select BOARD_ROMSIZE_KB_4096
- select GFXUMA
-
-config MAINBOARD_DIR
- default "asrock/e350m1"
-
-config MAINBOARD_PART_NUMBER
- default "E350M1"
-
-config HW_MEM_HOLE_SIZEK
- hex
- default 0x200000
-
-config MAX_CPUS
- int
- default 2
-
-config IRQ_SLOT_COUNT
- int
- default 11
-
-config ONBOARD_VGA_IS_PRIMARY
- bool
- default y
-
-config VGA_BIOS_ID
- string
- default "1002,9802"
-
-endif # BOARD_ASROCK_E350M1
diff --git a/src/mainboard/asrock/e350m1/Kconfig.name b/src/mainboard/asrock/e350m1/Kconfig.name
deleted file mode 100644
index a9a6ec506a..0000000000
--- a/src/mainboard/asrock/e350m1/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_ASROCK_E350M1
- bool "E350M1"
diff --git a/src/mainboard/asrock/e350m1/Makefile.inc b/src/mainboard/asrock/e350m1/Makefile.inc
deleted file mode 100644
index 549801d78f..0000000000
--- a/src/mainboard/asrock/e350m1/Makefile.inc
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-bootblock-y += bootblock.c
-
-romstage-y += buildOpts.c
-romstage-y += BiosCallOuts.c
-romstage-y += OemCustomize.c
-
-ramstage-y += buildOpts.c
-ramstage-y += BiosCallOuts.c
-ramstage-y += OemCustomize.c
diff --git a/src/mainboard/asrock/e350m1/OemCustomize.c b/src/mainboard/asrock/e350m1/OemCustomize.c
deleted file mode 100644
index 30e9f7e5c5..0000000000
--- a/src/mainboard/asrock/e350m1/OemCustomize.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <AGESA.h>
-#include <PlatformMemoryConfiguration.h>
-
-#include <northbridge/amd/agesa/state_machine.h>
-
-static const PCIe_PORT_DESCRIPTOR PortList[] = {
- // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
- {
- 0,
- PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
- HotplugDisabled,
- PcieGen2,
- PcieGen2,
- AspmL0sL1, 0)
- },
- // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
- {
- DESCRIPTOR_TERMINATE_LIST,
- PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
- HotplugDisabled,
- PcieGen2,
- PcieGen2,
- AspmL0sL1, 0)
- }
-};
-
-static const PCIe_DDI_DESCRIPTOR DdiList[] = {
- // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
- {
- 0,
- PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
- PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
- },
- // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
- {
- DESCRIPTOR_TERMINATE_LIST,
- PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
- PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
- }
-};
-
-static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
- .Flags = DESCRIPTOR_TERMINATE_LIST,
- .SocketId = 0,
- .PciePortList = PortList,
- .DdiLinkList = DdiList,
-};
-
-void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
-{
- InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
- InitEarly->GnbConfig.PsppPolicy = 0;
-}
-
-/*----------------------------------------------------------------------------------------
- * CUSTOMER OVERRIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-/*
- * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- * use its default conservative settings.
- */
-static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
- NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
- NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
- PSO_END
-};
-
-void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
-{
- InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
-}
diff --git a/src/mainboard/asrock/e350m1/OptionsIds.h b/src/mainboard/asrock/e350m1/OptionsIds.h
deleted file mode 100644
index 5a46df24e7..0000000000
--- a/src/mainboard/asrock/e350m1/OptionsIds.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/**
- * @file
- *
- * IDS Option File
- *
- * This file is used to switch on/off IDS features.
- *
- */
-#ifndef _OPTION_IDS_H_
-#define _OPTION_IDS_H_
-
-/**
- *
- * This file generates the defaults tables for the Integrated Debug Support
- * Module. The documented build options are imported from a user controlled
- * file for processing. The build options for the Integrated Debug Support
- * Module are listed below:
- *
- * IDSOPT_IDS_ENABLED
- * IDSOPT_ERROR_TRAP_ENABLED
- * IDSOPT_CONTROL_ENABLED
- * IDSOPT_TRACING_ENABLED
- * IDSOPT_PERF_ANALYSIS
- * IDSOPT_ASSERT_ENABLED
- * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
- *
- **/
-
-#define IDSOPT_IDS_ENABLED TRUE
-//#define IDSOPT_CONTROL_ENABLED TRUE
-//#define IDSOPT_TRACING_ENABLED TRUE
-//#define IDSOPT_PERF_ANALYSIS TRUE
-#define IDSOPT_ASSERT_ENABLED TRUE
-
-#endif
diff --git a/src/mainboard/asrock/e350m1/acpi/gpe.asl b/src/mainboard/asrock/e350m1/acpi/gpe.asl
deleted file mode 100644
index db500c0ee7..0000000000
--- a/src/mainboard/asrock/e350m1/acpi/gpe.asl
+++ /dev/null
@@ -1,54 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-Scope(\_GPE) { /* Start Scope GPE */
-
- /* Legacy PM event */
- Method(_L08) {
- /* DBGO("\\_GPE\\_L08\n") */
- }
-
- /* Temp warning (TWarn) event */
- Method(_L09) {
- /* DBGO("\\_GPE\\_L09\n") */
- /* Notify (\_TZ.TZ00, 0x80) */
- }
-
- /* USB controller PME# */
- Method(_L0B) {
- /* DBGO("\\_GPE\\_L0B\n") */
- Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* ExtEvent0 SCI event */
- Method(_L10) {
- /* DBGO("\\_GPE\\_L10\n") */
- }
-
-
- /* ExtEvent1 SCI event */
- Method(_L11) {
- /* DBGO("\\_GPE\\_L11\n") */
- }
-
- /* GPIO0 or GEvent8 event */
- Method(_L18) {
- /* DBGO("\\_GPE\\_L18\n") */
- Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* Azalia SCI event */
- Method(_L1B) {
- /* DBGO("\\_GPE\\_L1B\n") */
- Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
-} /* End Scope GPE */
diff --git a/src/mainboard/asrock/e350m1/acpi/routing.asl b/src/mainboard/asrock/e350m1/acpi/routing.asl
deleted file mode 100644
index 50cb070e91..0000000000
--- a/src/mainboard/asrock/e350m1/acpi/routing.asl
+++ /dev/null
@@ -1,382 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Routing is in System Bus scope */
-Scope(\_SB) {
- Name(PR0, Package(){
- /* NB devices */
- /* Bus 0, Dev 0 - RS780 Host Controller */
- /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
- Package(){0x0001FFFF, 0, INTC, 0 },
- Package(){0x0001FFFF, 1, INTD, 0 },
- /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
- Package(){0x0002FFFF, 0, INTC, 0 },
- Package(){0x0002FFFF, 1, INTD, 0 },
- Package(){0x0002FFFF, 2, INTA, 0 },
- Package(){0x0002FFFF, 3, INTB, 0 },
- /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
- Package(){0x0003FFFF, 0, INTD, 0 },
- Package(){0x0003FFFF, 1, INTA, 0 },
- Package(){0x0003FFFF, 2, INTB, 0 },
- Package(){0x0003FFFF, 3, INTC, 0 },
- /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
- Package(){0x0004FFFF, 0, INTA, 0 },
- Package(){0x0004FFFF, 1, INTB, 0 },
- Package(){0x0004FFFF, 2, INTC, 0 },
- Package(){0x0004FFFF, 3, INTD, 0 },
- /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
- Package(){0x0005FFFF, 0, INTB, 0 },
- Package(){0x0005FFFF, 1, INTC, 0 },
- Package(){0x0005FFFF, 2, INTD, 0 },
- Package(){0x0005FFFF, 3, INTA, 0 },
- /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
- Package(){0x0006FFFF, 0, INTC, 0 },
- Package(){0x0006FFFF, 1, INTD, 0 },
- Package(){0x0006FFFF, 2, INTA, 0 },
- Package(){0x0006FFFF, 3, INTB, 0 },
- /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
- Package(){0x0007FFFF, 0, INTD, 0 },
- Package(){0x0007FFFF, 1, INTA, 0 },
- Package(){0x0007FFFF, 2, INTB, 0 },
- Package(){0x0007FFFF, 3, INTC, 0 },
-
- Package(){0x0009FFFF, 0, INTB, 0 },
- Package(){0x0009FFFF, 1, INTC, 0 },
- Package(){0x0009FFFF, 2, INTD, 0 },
- Package(){0x0009FFFF, 3, INTA, 0 },
-
- Package(){0x000AFFFF, 0, INTC, 0 },
- Package(){0x000AFFFF, 1, INTD, 0 },
- Package(){0x000AFFFF, 2, INTA, 0 },
- Package(){0x000AFFFF, 3, INTB, 0 },
-
- Package(){0x000BFFFF, 0, INTD, 0 },
- Package(){0x000BFFFF, 1, INTA, 0 },
- Package(){0x000BFFFF, 2, INTB, 0 },
- Package(){0x000BFFFF, 3, INTC, 0 },
-
- Package(){0x000CFFFF, 0, INTA, 0 },
- Package(){0x000CFFFF, 1, INTB, 0 },
- Package(){0x000CFFFF, 2, INTC, 0 },
- Package(){0x000CFFFF, 3, INTD, 0 },
-
- /* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
- /* SB devices */
- /* Bus 0, Dev 17 - SATA controller #2 */
- /* Bus 0, Dev 18 - SATA controller #1 */
- Package(){0x0011FFFF, 0, INTD, 0 },
-
- /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
- * EHCI, dev 18, 19 func 2 */
- Package(){0x0012FFFF, 0, INTC, 0 },
- Package(){0x0012FFFF, 1, INTB, 0 },
-
- Package(){0x0013FFFF, 0, INTC, 0 },
- Package(){0x0013FFFF, 1, INTB, 0 },
-
- Package(){0x0016FFFF, 0, INTC, 0 },
- Package(){0x0016FFFF, 1, INTB, 0 },
-
- /* Package(){0x0014FFFF, 1, INTA, 0 }, */
-
- /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
- Package(){0x0014FFFF, 0, INTA, 0 },
- Package(){0x0014FFFF, 1, INTB, 0 },
- Package(){0x0014FFFF, 2, INTC, 0 },
- Package(){0x0014FFFF, 3, INTD, 0 },
-
- Package(){0x0015FFFF, 0, INTA, 0 },
- Package(){0x0015FFFF, 1, INTB, 0 },
- Package(){0x0015FFFF, 2, INTC, 0 },
- Package(){0x0015FFFF, 3, INTD, 0 },
- })
-
- Name(APR0, Package(){
- /* NB devices in APIC mode */
- /* Bus 0, Dev 0 - RS780 Host Controller */
-
- /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
- Package(){0x0001FFFF, 0, 0, 18 },
- Package(){0x0001FFFF, 1, 0, 19 },
-
- /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
- Package(){0x0002FFFF, 0, 0, 18 },
- /* Package(){0x0002FFFF, 1, 0, 19 }, */
- /* Package(){0x0002FFFF, 2, 0, 16 }, */
- /* Package(){0x0002FFFF, 3, 0, 17 }, */
-
- /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
- Package(){0x0003FFFF, 0, 0, 19 },
- Package(){0x0003FFFF, 1, 0, 16 },
- Package(){0x0003FFFF, 2, 0, 17 },
- Package(){0x0003FFFF, 3, 0, 18 },
-
- /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
- Package(){0x0004FFFF, 0, 0, 16 },
- Package(){0x0004FFFF, 1, 0, 17 },
- Package(){0x0004FFFF, 2, 0, 18 },
- Package(){0x0004FFFF, 3, 0, 19 },
-
- /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
- Package(){0x0005FFFF, 0, 0, 17 },
- Package(){0x0005FFFF, 1, 0, 18 },
- Package(){0x0005FFFF, 2, 0, 19 },
- Package(){0x0005FFFF, 3, 0, 16 },
-
- /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
- Package(){0x0006FFFF, 0, 0, 18 },
- Package(){0x0006FFFF, 1, 0, 19 },
- Package(){0x0006FFFF, 2, 0, 16 },
- Package(){0x0006FFFF, 3, 0, 17 },
-
- /* Bus 0, Dev 7 - PCIe Bridge for network card */
- Package(){0x0007FFFF, 0, 0, 19 },
- Package(){0x0007FFFF, 1, 0, 16 },
- Package(){0x0007FFFF, 2, 0, 17 },
- Package(){0x0007FFFF, 3, 0, 18 },
-
- /* Bus 0, Dev 9 - PCIe Bridge for network card */
- Package(){0x0009FFFF, 0, 0, 17 },
- Package(){0x0009FFFF, 1, 0, 16 },
- Package(){0x0009FFFF, 2, 0, 17 },
- Package(){0x0009FFFF, 3, 0, 18 },
- /* Bus 0, Dev A - PCIe Bridge for network card */
- Package(){0x000AFFFF, 0, 0, 18 },
- Package(){0x000AFFFF, 1, 0, 16 },
- Package(){0x000AFFFF, 2, 0, 17 },
- Package(){0x000AFFFF, 3, 0, 18 },
- /* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
- /* SB devices in APIC mode */
- /* Bus 0, Dev 17 - SATA controller #2 */
- /* Bus 0, Dev 18 - SATA controller #1 */
- Package(){0x0011FFFF, 0, 0, 19 },
-
- /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
- * EHCI, dev 18, 19 func 2 */
- Package(){0x0012FFFF, 0, 0, 18 },
- Package(){0x0012FFFF, 1, 0, 17 },
- /* Package(){0x0012FFFF, 2, 0, 18 }, */
-
- Package(){0x0013FFFF, 0, 0, 18 },
- Package(){0x0013FFFF, 1, 0, 17 },
- /* Package(){0x0013FFFF, 2, 0, 16 }, */
-
- /* Package(){0x00140000, 0, 0, 16 }, */
-
- Package(){0x0016FFFF, 0, 0, 18 },
- Package(){0x0016FFFF, 1, 0, 17 },
-
- /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
- Package(){0x0014FFFF, 0, 0, 16 },
- Package(){0x0014FFFF, 1, 0, 17 },
- Package(){0x0014FFFF, 2, 0, 18 },
- Package(){0x0014FFFF, 3, 0, 19 },
- /* Package(){0x00140004, 2, 0, 18 }, */
- /* Package(){0x00140004, 3, 0, 19 }, */
- /* Package(){0x00140005, 1, 0, 17 }, */
- /* Package(){0x00140006, 1, 0, 17 }, */
-
- /* TODO: PCIe */
- Package(){0x0015FFFF, 0, 0, 16 },
- Package(){0x0015FFFF, 1, 0, 17 },
- Package(){0x0015FFFF, 2, 0, 18 },
- Package(){0x0015FFFF, 3, 0, 19 },
- })
-
- Name(PR1, Package(){
- /* Internal graphics - RS780 VGA, Bus1, Dev5 */
- Package(){0x0005FFFF, 0, INTA, 0 },
- Package(){0x0005FFFF, 1, INTB, 0 },
- Package(){0x0005FFFF, 2, INTC, 0 },
- Package(){0x0005FFFF, 3, INTD, 0 },
- })
- Name(APR1, Package(){
- /* Internal graphics - RS780 VGA, Bus1, Dev5 */
- Package(){0x0005FFFF, 0, 0, 18 },
- Package(){0x0005FFFF, 1, 0, 19 },
- /* Package(){0x0005FFFF, 2, 0, 20 }, */
- /* Package(){0x0005FFFF, 3, 0, 17 }, */
- })
-
- Name(PS2, Package(){
- /* The external GFX - Hooked to PCIe slot 2 */
- Package(){0x0000FFFF, 0, INTC, 0 },
- Package(){0x0000FFFF, 1, INTD, 0 },
- Package(){0x0000FFFF, 2, INTA, 0 },
- Package(){0x0000FFFF, 3, INTB, 0 },
- })
- Name(APS2, Package(){
- /* The external GFX - Hooked to PCIe slot 2 */
- Package(){0x0000FFFF, 0, 0, 18 },
- Package(){0x0000FFFF, 1, 0, 19 },
- Package(){0x0000FFFF, 2, 0, 16 },
- Package(){0x0000FFFF, 3, 0, 17 },
- })
-
- Name(PS4, Package(){
- /* PCIe slot - Hooked to PCIe slot 4 */
- Package(){0x0000FFFF, 0, INTA, 0 },
- Package(){0x0000FFFF, 1, INTB, 0 },
- Package(){0x0000FFFF, 2, INTC, 0 },
- Package(){0x0000FFFF, 3, INTD, 0 },
- })
- Name(APS4, Package(){
- /* PCIe slot - Hooked to PCIe slot 4 */
- Package(){0x0000FFFF, 0, 0, 16 },
- Package(){0x0000FFFF, 1, 0, 17 },
- Package(){0x0000FFFF, 2, 0, 18 },
- Package(){0x0000FFFF, 3, 0, 19 },
- })
-
- Name(PS5, Package(){
- /* PCIe slot - Hooked to PCIe slot 5 */
- Package(){0x0000FFFF, 0, INTB, 0 },
- Package(){0x0000FFFF, 1, INTC, 0 },
- Package(){0x0000FFFF, 2, INTD, 0 },
- Package(){0x0000FFFF, 3, INTA, 0 },
- })
- Name(APS5, Package(){
- /* PCIe slot - Hooked to PCIe slot 5 */
- Package(){0x0000FFFF, 0, 0, 17 },
- Package(){0x0000FFFF, 1, 0, 18 },
- Package(){0x0000FFFF, 2, 0, 19 },
- Package(){0x0000FFFF, 3, 0, 16 },
- })
-
- Name(PS6, Package(){
- /* PCIe slot - Hooked to PCIe slot 6 */
- Package(){0x0000FFFF, 0, INTC, 0 },
- Package(){0x0000FFFF, 1, INTD, 0 },
- Package(){0x0000FFFF, 2, INTA, 0 },
- Package(){0x0000FFFF, 3, INTB, 0 },
- })
- Name(APS6, Package(){
- /* PCIe slot - Hooked to PCIe slot 6 */
- Package(){0x0000FFFF, 0, 0, 18 },
- Package(){0x0000FFFF, 1, 0, 19 },
- Package(){0x0000FFFF, 2, 0, 16 },
- Package(){0x0000FFFF, 3, 0, 17 },
- })
-
- Name(PS7, Package(){
- /* The onboard Ethernet chip - Hooked to PCIe slot 7 */
- Package(){0x0000FFFF, 0, INTD, 0 },
- Package(){0x0000FFFF, 1, INTA, 0 },
- Package(){0x0000FFFF, 2, INTB, 0 },
- Package(){0x0000FFFF, 3, INTC, 0 },
- })
- Name(APS7, Package(){
- /* The onboard Ethernet chip - Hooked to PCIe slot 7 */
- Package(){0x0000FFFF, 0, 0, 19 },
- Package(){0x0000FFFF, 1, 0, 16 },
- Package(){0x0000FFFF, 2, 0, 17 },
- Package(){0x0000FFFF, 3, 0, 18 },
- })
-
- Name(PS9, Package(){
- /* PCIe slot - Hooked to PCIe slot 9 */
- Package(){0x0000FFFF, 0, INTD, 0 },
- Package(){0x0000FFFF, 1, INTA, 0 },
- Package(){0x0000FFFF, 2, INTB, 0 },
- Package(){0x0000FFFF, 3, INTC, 0 },
- })
- Name(APS9, Package(){
- /* PCIe slot - Hooked to PCIe slot 9 */
- Package(){0x0000FFFF, 0, 0, 17 },
- Package(){0x0000FFFF, 1, 0, 18 },
- Package(){0x0000FFFF, 2, 0, 19 },
- Package(){0x0000FFFF, 3, 0, 16 },
- })
-
- Name(PSA, Package(){
- /* PCIe slot - Hooked to PCIe slot 10 */
- Package(){0x0000FFFF, 0, INTD, 0 },
- Package(){0x0000FFFF, 1, INTA, 0 },
- Package(){0x0000FFFF, 2, INTB, 0 },
- Package(){0x0000FFFF, 3, INTC, 0 },
- })
- Name(APSA, Package(){
- /* PCIe slot - Hooked to PCIe slot 10 */
- Package(){0x0000FFFF, 0, 0, 18 },
- Package(){0x0000FFFF, 1, 0, 19 },
- Package(){0x0000FFFF, 2, 0, 16 },
- Package(){0x0000FFFF, 3, 0, 17 },
- })
-
- Name(PE0, Package(){
- /* PCIe slot - Hooked to PCIe slot 10 */
- Package(){0x0000FFFF, 0, INTA, 0 },
- Package(){0x0000FFFF, 1, INTB, 0 },
- Package(){0x0000FFFF, 2, INTC, 0 },
- Package(){0x0000FFFF, 3, INTD, 0 },
- })
- Name(APE0, Package(){
- /* PCIe slot - Hooked to PCIe */
- Package(){0x0000FFFF, 0, 0, 16 },
- Package(){0x0000FFFF, 1, 0, 17 },
- Package(){0x0000FFFF, 2, 0, 18 },
- Package(){0x0000FFFF, 3, 0, 19 },
- })
-
- Name(PE1, Package(){
- /* PCIe slot - Hooked to PCIe slot 10 */
- Package(){0x0000FFFF, 0, INTB, 0 },
- Package(){0x0000FFFF, 1, INTC, 0 },
- Package(){0x0000FFFF, 2, INTD, 0 },
- Package(){0x0000FFFF, 3, INTA, 0 },
- })
- Name(APE1, Package(){
- /* PCIe slot - Hooked to PCIe */
- Package(){0x0000FFFF, 0, 0, 17 },
- Package(){0x0000FFFF, 1, 0, 18 },
- Package(){0x0000FFFF, 2, 0, 19 },
- Package(){0x0000FFFF, 3, 0, 16 },
- })
-
- Name(PE2, Package(){
- /* PCIe slot - Hooked to PCIe slot 10 */
- Package(){0x0000FFFF, 0, INTC, 0 },
- Package(){0x0000FFFF, 1, INTD, 0 },
- Package(){0x0000FFFF, 2, INTA, 0 },
- Package(){0x0000FFFF, 3, INTB, 0 },
- })
- Name(APE2, Package(){
- /* PCIe slot - Hooked to PCIe */
- Package(){0x0000FFFF, 0, 0, 18 },
- Package(){0x0000FFFF, 1, 0, 19 },
- Package(){0x0000FFFF, 2, 0, 16 },
- Package(){0x0000FFFF, 3, 0, 17 },
- })
-
- Name(PE3, Package(){
- /* PCIe slot - Hooked to PCIe slot 10 */
- Package(){0x0000FFFF, 0, INTD, 0 },
- Package(){0x0000FFFF, 1, INTA, 0 },
- Package(){0x0000FFFF, 2, INTB, 0 },
- Package(){0x0000FFFF, 3, INTC, 0 },
- })
- Name(APE3, Package(){
- /* PCIe slot - Hooked to PCIe */
- Package(){0x0000FFFF, 0, 0, 19 },
- Package(){0x0000FFFF, 1, 0, 16 },
- Package(){0x0000FFFF, 2, 0, 17 },
- Package(){0x0000FFFF, 3, 0, 18 },
- })
-
- Name(PCIB, Package(){
- /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
- Package(){0x0005FFFF, 0, 0, 0x14 },
- Package(){0x0005FFFF, 1, 0, 0x15 },
- Package(){0x0005FFFF, 2, 0, 0x16 },
- Package(){0x0005FFFF, 3, 0, 0x17 },
- Package(){0x0006FFFF, 0, 0, 0x15 },
- Package(){0x0006FFFF, 1, 0, 0x16 },
- Package(){0x0006FFFF, 2, 0, 0x17 },
- Package(){0x0006FFFF, 3, 0, 0x14 },
- Package(){0x0007FFFF, 0, 0, 0x16 },
- Package(){0x0007FFFF, 1, 0, 0x17 },
- Package(){0x0007FFFF, 2, 0, 0x14 },
- Package(){0x0007FFFF, 3, 0, 0x15 },
- })
-}
diff --git a/src/mainboard/asrock/e350m1/acpi/sata.asl b/src/mainboard/asrock/e350m1/acpi/sata.asl
deleted file mode 100644
index 6d9ff03005..0000000000
--- a/src/mainboard/asrock/e350m1/acpi/sata.asl
+++ /dev/null
@@ -1,132 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* simple name description */
-
-/*
-Scope (_SB) {
- Device(PCI0) {
- Device(SATA) {
- Name(_ADR, 0x00110000)
- #include "sata.asl"
- }
- }
-}
-*/
-
-Name(STTM, Buffer(20) {
- 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
- 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
- 0x1f, 0x00, 0x00, 0x00
-})
-
-/* Start by clearing the PhyRdyChg bits */
-Method(_INI) {
- \_GPE._L1F()
-}
-
-Device(PMRY)
-{
- Name(_ADR, 0)
- Method(_GTM, 0x0, NotSerialized) {
- Return(STTM)
- }
- Method(_STM, 0x3, NotSerialized) {}
-
- Device(PMST) {
- Name(_ADR, 0)
- Method(_STA,0) {
- if (P0IS > 0) {
- return (0x0F) /* sata is visible */
- }
- else {
- return (0x00) /* sata is missing */
- }
- }
- }/* end of PMST */
-
- Device(PSLA)
- {
- Name(_ADR, 1)
- Method(_STA,0) {
- if (P1IS > 0) {
- return (0x0F) /* sata is visible */
- }
- else {
- return (0x00) /* sata is missing */
- }
- }
- } /* end of PSLA */
-} /* end of PMRY */
-
-
-Device(SEDY)
-{
- Name(_ADR, 1) /* IDE Scondary Channel */
- Method(_GTM, 0x0, NotSerialized) {
- Return(STTM)
- }
- Method(_STM, 0x3, NotSerialized) {}
-
- Device(SMST)
- {
- Name(_ADR, 0)
- Method(_STA,0) {
- if (P2IS > 0) {
- return (0x0F) /* sata is visible */
- }
- else {
- return (0x00) /* sata is missing */
- }
- }
- } /* end of SMST */
-
- Device(SSLA)
- {
- Name(_ADR, 1)
- Method(_STA,0) {
- if (P3IS > 0) {
- return (0x0F) /* sata is visible */
- }
- else {
- return (0x00) /* sata is missing */
- }
- }
- } /* end of SSLA */
-} /* end of SEDY */
-
-/* SATA Hot Plug Support */
-Scope(\_GPE) {
- Method(_L1F,0x0,NotSerialized) {
- if (\_SB.P0PR) {
- if (\_SB.P0IS > 0) {
- sleep(32)
- }
- Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
- \_SB.P0PR = 1
- }
-
- if (\_SB.P1PR) {
- if (\_SB.P1IS > 0) {
- sleep(32)
- }
- Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
- \_SB.P1PR = 1
- }
-
- if (\_SB.P2PR) {
- if (\_SB.P2IS > 0) {
- sleep(32)
- }
- Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
- \_SB.P2PR = 1
- }
-
- if (\_SB.P3PR) {
- if (\_SB.P3IS > 0) {
- sleep(32)
- }
- Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
- \_SB.P3PR = 1
- }
- }
-}
diff --git a/src/mainboard/asrock/e350m1/acpi/sleep.asl b/src/mainboard/asrock/e350m1/acpi/sleep.asl
deleted file mode 100644
index 3b6fd02055..0000000000
--- a/src/mainboard/asrock/e350m1/acpi/sleep.asl
+++ /dev/null
@@ -1,88 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Wake status package */
-Name(WKST,Package(){Zero, Zero})
-
-/*
-* \_PTS - Prepare to Sleep method
-*
-* Entry:
-* Arg0=The value of the sleeping state S1=1, S2=2, etc
-*
-* Exit:
-* -none-
-*
-* The _PTS control method is executed at the beginning of the sleep process
-* for S1-S5. The sleeping value is passed to the _PTS control method. This
-* control method may be executed a relatively long time before entering the
-* sleep state and the OS may abort the operation without notification to
-* the ACPI driver. This method cannot modify the configuration or power
-* state of any device in the system.
-*/
-Method(\_PTS, 1) {
- /* DBGO("\\_PTS\n") */
- /* DBGO("From S0 to S") */
- /* DBGO(Arg0) */
- /* DBGO("\n") */
-
- /* Don't allow PCIRST# to reset USB */
- if (Arg0 == 3){
- URRE = 0
- }
-
- /* Clear sleep SMI status flag and enable sleep SMI trap. */
- /*CSSM = 1
- SSEN = 1*/
-
- /* On older chips, clear PciExpWakeDisEn */
- /*if (\_SB.SBRI <= 0x13) {
- * \_SB.PWDE = 0
- *}
- */
-
- /* Clear wake status structure. */
- WKST [0] = 0
- WKST [1] = 0
-} /* End Method(\_PTS) */
-
-/*
-* \_WAK System Wake method
-*
-* Entry:
-* Arg0=The value of the sleeping state S1=1, S2=2
-*
-* Exit:
-* Return package of 2 DWords
-* Dword 1 - Status
-* 0x00000000 wake succeeded
-* 0x00000001 Wake was signaled but failed due to lack of power
-* 0x00000002 Wake was signaled but failed due to thermal condition
-* Dword 2 - Power Supply state
-* if non-zero the effective S-state the power supply entered
-*/
-Method(\_WAK, 1) {
- /* DBGO("\\_WAK\n") */
- /* DBGO("From S") */
- /* DBGO(Arg0) */
- /* DBGO(" to S0\n") */
-
- /* Re-enable HPET */
- HPDE = 1
-
- /* Restore PCIRST# so it resets USB */
- if (Arg0 == 3){
- URRE = 1
- }
-
- /* Arbitrarily clear PciExpWakeStatus */
- Local1 = PWST
- PWST = Local1
-
- /* if (DeRefOf(WKST [0])) {
- * WKST [1] = 0
- * } else {
- * WKST [1] = Arg0
- * }
- */
- Return(WKST)
-} /* End Method(\_WAK) */
diff --git a/src/mainboard/asrock/e350m1/acpi/superio.asl b/src/mainboard/asrock/e350m1/acpi/superio.asl
deleted file mode 100644
index 55b1db5b11..0000000000
--- a/src/mainboard/asrock/e350m1/acpi/superio.asl
+++ /dev/null
@@ -1,3 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/asrock/e350m1/acpi/usb_oc.asl b/src/mainboard/asrock/e350m1/acpi/usb_oc.asl
deleted file mode 100644
index e4ed275617..0000000000
--- a/src/mainboard/asrock/e350m1/acpi/usb_oc.asl
+++ /dev/null
@@ -1,148 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* USB overcurrent mapping pins. */
-Name(UOM0, 0)
-Name(UOM1, 2)
-Name(UOM2, 0)
-Name(UOM3, 7)
-Name(UOM4, 2)
-Name(UOM5, 2)
-Name(UOM6, 6)
-Name(UOM7, 2)
-Name(UOM8, 6)
-Name(UOM9, 6)
-
-Method(UCOC, 0) {
- Sleep(20)
- CMTI = 0x13
- GPSL = 0
-}
-
-/* USB Port 0 overcurrent uses Gpm 0 */
-If (UOM0 <= 9) {
- Scope (\_GPE) {
- Method (_L13) {
- UCOC()
- if (GPB0 == PLC0) {
- PLC0 = ~PLC0
- \_SB.PT0D = PLC0
- }
- }
- }
-}
-
-/* USB Port 1 overcurrent uses Gpm 1 */
-If (UOM1 <= 9) {
- Scope (\_GPE) {
- Method (_L14) {
- UCOC()
- if (GPB1 == PLC1) {
- PLC1 = ~PLC1
- \_SB.PT1D = PLC1
- }
- }
- }
-}
-
-/* USB Port 2 overcurrent uses Gpm 2 */
-If (UOM2 <= 9) {
- Scope (\_GPE) {
- Method (_L15) {
- UCOC()
- if (GPB2 == PLC2) {
- PLC2 = ~PLC2
- \_SB.PT2D = PLC2
- }
- }
- }
-}
-
-/* USB Port 3 overcurrent uses Gpm 3 */
-If (UOM3 <= 9) {
- Scope (\_GPE) {
- Method (_L16) {
- UCOC()
- if (GPB3 == PLC3) {
- PLC3 = ~PLC3
- \_SB.PT3D = PLC3
- }
- }
- }
-}
-
-/* USB Port 4 overcurrent uses Gpm 4 */
-If (UOM4 <= 9) {
- Scope (\_GPE) {
- Method (_L19) {
- UCOC()
- if (GPB4 == PLC4) {
- PLC4 = ~PLC4
- \_SB.PT4D = PLC4
- }
- }
- }
-}
-
-/* USB Port 5 overcurrent uses Gpm 5 */
-If (UOM5 <= 9) {
- Scope (\_GPE) {
- Method (_L1A) {
- UCOC()
- if (GPB5 == PLC5) {
- PLC5 = ~PLC5
- \_SB.PT5D = PLC5
- }
- }
- }
-}
-
-/* USB Port 6 overcurrent uses Gpm 6 */
-If (UOM6 <= 9) {
- Scope (\_GPE) {
- /* Method (_L1C) { */
- Method (_L06) {
- UCOC()
- if (GPB6 == PLC6) {
- PLC6 = ~PLC6
- \_SB.PT6D = PLC6
- }
- }
- }
-}
-
-/* USB Port 7 overcurrent uses Gpm 7 */
-If (UOM7 <= 9) {
- Scope (\_GPE) {
- /* Method (_L1D) { */
- Method (_L07) {
- UCOC()
- if (GPB7 == PLC7) {
- PLC7 = ~PLC7
- \_SB.PT7D = PLC7
- }
- }
- }
-}
-
-/* USB Port 8 overcurrent uses Gpm 8 */
-If (UOM8 <= 9) {
- Scope (\_GPE) {
- Method (_L17) {
- if (G8IS == PLC8) {
- PLC8 = ~PLC8
- \_SB.PT8D = PLC8
- }
- }
- }
-}
-
-/* USB Port 9 overcurrent uses Gpm 9 */
-If (UOM9 <= 9) {
- Scope (\_GPE) {
- Method (_L0E) {
- if (G9IS == 0) {
- \_SB.PT9D = 1
- }
- }
- }
-}
diff --git a/src/mainboard/asrock/e350m1/board_info.txt b/src/mainboard/asrock/e350m1/board_info.txt
deleted file mode 100644
index 76563ca24c..0000000000
--- a/src/mainboard/asrock/e350m1/board_info.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Category: mini
-Board URL: http://www.asrock.com/mb/overview.asp?Model=E350M1
-ROM package: DIP8
-ROM protocol: SPI
-ROM socketed: y
-Flashrom support: y
-Release year: 2011
diff --git a/src/mainboard/asrock/e350m1/bootblock.c b/src/mainboard/asrock/e350m1/bootblock.c
deleted file mode 100644
index 210a0143cf..0000000000
--- a/src/mainboard/asrock/e350m1/bootblock.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <bootblock_common.h>
-#include <superio/nuvoton/common/nuvoton.h>
-#include <superio/nuvoton/nct5572d/nct5572d.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, NCT5572D_SP1)
-
-void bootblock_mainboard_early_init(void)
-{
- nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-}
diff --git a/src/mainboard/asrock/e350m1/buildOpts.c b/src/mainboard/asrock/e350m1/buildOpts.c
deleted file mode 100644
index 1c4d62c250..0000000000
--- a/src/mainboard/asrock/e350m1/buildOpts.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Select the CPU family */
-#define INSTALL_FAMILY_14_SUPPORT TRUE
-
-/* Select the CPU socket type */
-#define INSTALL_FT1_SOCKET_SUPPORT TRUE
-
-/* Agesa optional capabilities selection */
-#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE
-#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
-#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE
-#define BLDOPT_REMOVE_ECC_SUPPORT FALSE
-#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE
-#define BLDOPT_REMOVE_WHEA TRUE
-
-#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1
-
-#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
-#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
-#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE
-#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE
-
-/* Agesa configuration values selection */
-#include <AGESA.h>
-
-/* Include the files that instantiate the configuration definitions */
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "AdvancedApi.h"
-#include "heapManager.h"
-#include "CreateStruct.h"
-#include "cpuFeatures.h"
-#include "Table.h"
-#include "cpuEarlyInit.h"
-#include "cpuLateInit.h"
-#include "GnbInterface.h"
-
-/* Instantiate all solution relevant data */
-#include <PlatformInstall.h>
diff --git a/src/mainboard/asrock/e350m1/cmos.layout b/src/mainboard/asrock/e350m1/cmos.layout
deleted file mode 100644
index c7cd5e6957..0000000000
--- a/src/mainboard/asrock/e350m1/cmos.layout
+++ /dev/null
@@ -1,38 +0,0 @@
-#*****************************************************************************
-# SPDX-License-Identifier: GPL-2.0-only
-
-#*****************************************************************************
-
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-400 2 e 3 power_on_after_fail
-412 4 e 6 debug_level
-444 1 e 1 nmi
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-3 0 Off
-3 1 On
-3 2 Last
-4 0 Fallback
-4 1 Normal
-6 5 Notice
-6 6 Info
-6 7 Debug
-6 8 Spew
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/asrock/e350m1/devicetree.cb b/src/mainboard/asrock/e350m1/devicetree.cb
deleted file mode 100644
index 1fb8b20ca4..0000000000
--- a/src/mainboard/asrock/e350m1/devicetree.cb
+++ /dev/null
@@ -1,130 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-chip northbridge/amd/agesa/family14/root_complex
- device cpu_cluster 0 on
- chip cpu/amd/agesa/family14
- device lapic 0 on end
- end
- end
- device domain 0 on
- subsystemid 0x1022 0x1510 inherit
- chip northbridge/amd/agesa/family14
- device pci 0.0 on end # Root Complex
- device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
-
- device pci 1.1 on end # Internal HDMI Audio
- device pci 4.0 on end # PCIE P2P bridge 0x9604
- device pci 5.0 off end # PCIE P2P bridge 0x9605
- device pci 6.0 off end # PCIE P2P bridge 0x9606
- device pci 7.0 off end # PCIE P2P bridge 0x9607
- device pci 8.0 off end # NB/SB Link P2P bridge
- end # agesa northbridge
-
- chip southbridge/amd/cimx/sb800
- device pci 11.0 on end # SATA
- device pci 12.0 on end # USB
- device pci 12.2 on end # USB
- device pci 13.0 on end # USB
- device pci 13.2 on end # USB
- device pci 14.0 on end # SM
- device pci 14.1 on end # IDE 0x439c
- device pci 14.2 on end # HDA 0x4383
- device pci 14.3 on # LPC
- chip superio/nuvoton/nct5572d
- device pnp 2e.0 off end # FDC; not externally available on the NCT5572D, but on the die
- device pnp 2e.1 off end # LPT1; same as FDC
- device pnp 2e.2 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 off # IR
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.5 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- end
- device pnp 2e.6 off # CIR
- io 0x60 = 0x100
- irq 0x70 = 0
- end
- device pnp 2e.107 off end # GPIO6
- device pnp 2e.207 off end # GPIO7
- device pnp 2e.307 on # GPIO8
- irq 0x23 = 0x28
- irq 0xe4 = 0xbf
- irq 0xed = 0x27
- end
- device pnp 2e.407 off end # GPIO9
- device pnp 2e.8 off end # WDT
- device pnp 2e.009 on # GPIO2
- irq 0x2a = 0x42
- irq 0xe0 = 0xe3
- end
- device pnp 2e.109 off end # GPIO3
- device pnp 2e.209 off end # GPIO4
- device pnp 2e.309 off end # GPIO5
- device pnp 2e.a on # ACPI
- irq 0xe7 = 0x10
- end
- device pnp 2e.b on # HW Monitor
- io 0x60 = 0x290
- io 0x62 = 0x0000 # SB-TSI currently not implemented
- irq 0x70 = 5
- end
- device pnp 2e.c off end # PECI
- device pnp 2e.d on # SUSLED
- irq 0xec = 0x90
- end
- device pnp 2e.e off # CIRWKUP
- io 0x60 = 0x0000
- irq 0x70 = 0
- end
- device pnp 2e.f off end # GPIO_PP_OD
- end
- end #LPC
- device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
- device pci 14.5 on end # USB 2
- device pci 15.0 on end # PCIe PortA
- device pci 15.1 on end # PCIe PortB: NIC
- device pci 15.2 on end # PCIe PortC: USB3
- device pci 15.3 off end # PCIe PortD
- device pci 16.0 on end # OHCI mPCIe
- device pci 16.2 on end # EHCI mPCIe
-
- # gpp_configuration options
- #0000: PortA lanes[3:0]
- #0001: N/A
- #0010: PortA lanes[1:0], PortB lanes[3:2]
- #0011: PortA lanes[1:0], PortB lane2, PortC lane3
- #0100: PortA lane0, PortB lane1, PortC lane2, PortD lane3.
- register "gpp_configuration" = "4"
-
- register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
- end #southbridge/amd/cimx/sb800
-
- chip northbridge/amd/agesa/family14
-
- # These seem unnecessary
- device pci 18.0 on end
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- device pci 18.4 on end
- device pci 18.5 on end
- device pci 18.6 on end
- device pci 18.7 on end
-
- register "spdAddrLookup" = "
- {
- { {0xA0, 0xA4}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
- { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
- }"
-
- end # agesa northbridge
-
- end #domain
-end #northbridge/amd/agesa/family14/root_complex
diff --git a/src/mainboard/asrock/e350m1/dsdt.asl b/src/mainboard/asrock/e350m1/dsdt.asl
deleted file mode 100644
index 226728052f..0000000000
--- a/src/mainboard/asrock/e350m1/dsdt.asl
+++ /dev/null
@@ -1,46 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* DefinitionBlock Statement */
-#include <acpi/acpi.h>
-DefinitionBlock (
- "dsdt.aml",
- "DSDT",
- ACPI_DSDT_REV_2,
- OEM_ID,
- ACPI_TABLE_CREATOR,
- 0x00010001 /* OEM Revision */
- )
-{ /* Start of ASL file */
- #include <acpi/dsdt_top.asl>
-
- #include <cpu/amd/agesa/family14/acpi/cpu.asl>
-
- #include "acpi/routing.asl"
-
- Scope(\_SB) {
- /* global utility methods expected within the \_SB scope */
- #include <arch/x86/acpi/globutil.asl>
-
- Device(PCI0) {
-
- /* Describe the AMD Northbridge */
- #include <northbridge/amd/agesa/family14/acpi/northbridge.asl>
-
- /* Describe the AMD Fusion Controller Hub Southbridge */
- #include <southbridge/amd/cimx/sb800/acpi/fch.asl>
-
- }
- } /* End Scope(_SB) */
-
- #include "acpi/superio.asl"
-
- /* Contains the supported sleep states for this chipset */
- #include <southbridge/amd/common/acpi/sleepstates.asl>
-
- /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
- #include "acpi/sleep.asl"
-
- #include "acpi/gpe.asl"
- #include "acpi/usb_oc.asl"
-}
-/* End of ASL file */
diff --git a/src/mainboard/asrock/e350m1/irq_tables.c b/src/mainboard/asrock/e350m1/irq_tables.c
deleted file mode 100644
index 06880eb107..0000000000
--- a/src/mainboard/asrock/e350m1/irq_tables.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <console/console.h>
-#include <commonlib/bsd/helpers.h>
-#include <device/pci_def.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
- u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
- u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
- u8 slot, u8 rfu)
-{
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = bitmap0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = bitmap1;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = bitmap2;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = bitmap3;
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
-}
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- struct irq_routing_table *pirq;
- struct irq_info *pirq_info;
- u32 slot_num;
- u8 *v;
-
- u8 sum = 0;
- int i;
-
- /* Align the table to be 16 byte aligned. */
- addr = ALIGN_UP(addr, 16);
-
- /* This table must be between 0xf0000 & 0x100000 */
- printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
- pirq = (void *)(addr);
- v = (u8 *) (addr);
-
- pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
-
- pirq->rtr_bus = 0;
- pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
-
- pirq->exclusive_irqs = 0;
-
- pirq->rtr_vendor = 0x1002;
- pirq->rtr_device = 0x4384;
-
- pirq->miniport_data = 0;
-
- memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
- pirq_info = (void *)(&pirq->checksum + 1);
- slot_num = 0;
-
- /* pci bridge */
- write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
- 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
- 0);
- pirq_info++;
-
- slot_num++;
-
- pirq->size = 32 + 16 * slot_num;
-
- for (i = 0; i < pirq->size; i++)
- sum += v[i];
-
- sum = pirq->checksum - sum;
-
- if (sum != pirq->checksum) {
- pirq->checksum = sum;
- }
-
- printk(BIOS_INFO, "%s done.\n", __func__);
-
- return (unsigned long)pirq_info;
-}
diff --git a/src/mainboard/asrock/e350m1/mainboard.c b/src/mainboard/asrock/e350m1/mainboard.c
deleted file mode 100644
index 68255f9946..0000000000
--- a/src/mainboard/asrock/e350m1/mainboard.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <amdblocks/acpimmio.h>
-#include <device/device.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <device/mmio.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-
-static const u8 mainboard_intr_data[] = {
- [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, /* INTA# - INTH# */
- [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, /* Misc-nil, 0, 1, 2, INT from Serial irq */
- [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x10, 0x11, 0x12, 0x13
-};
-
-/* PIRQ Setup */
-static void pirq_setup(void)
-{
- intr_data_ptr = mainboard_intr_data;
-}
-
-/**********************************************
- * Enable the dedicated functions of the board.
- **********************************************/
-static void mainboard_enable(struct device *dev)
-{
- pirq_setup();
-
- /* Power off unused clock pins of GPP PCIe devices
- * GPP CLK0 connected to unpopulated mini PCIe slot
- * GPP CLK1 connected to ethernet chip
- */
- misc_write8(0, 0xff);
- /* GPP CLK2 connected to the external USB3 controller */
- misc_write8(1, 0x0f);
- misc_write8(2, 0);
- misc_write8(3, 0);
- /* SLT_GFX_CLK connected to PCIe slot */
- misc_write8(4, 0xf0);
-
- /*
- * Initialize ASF registers to an arbitrary address because someone
- * long ago set things up this way inside the SPD read code. The
- * SPD read code has been made generic and moved out of the board
- * directory, so the ASF init is being done here.
- */
- pm_write8(0x29, 0x80);
- pm_write8(0x28, 0x61);
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/asrock/e350m1/platform_cfg.h b/src/mainboard/asrock/e350m1/platform_cfg.h
deleted file mode 100644
index 6994575985..0000000000
--- a/src/mainboard/asrock/e350m1/platform_cfg.h
+++ /dev/null
@@ -1,202 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _PLATFORM_CFG_H_
-#define _PLATFORM_CFG_H_
-
-/**
- * @def BIOS_SIZE
- * BIOS_SIZE_{1,2,4,8,16}M
- *
- * In SB800, default ROM size is 1M Bytes, if your platform ROM
- * bigger than 1M you have to set the ROM size outside CIMx module and
- * before AGESA module get call.
- */
-#ifndef BIOS_SIZE
-#define BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1)
-#endif /* BIOS_SIZE */
-
-/**
- * @def SPREAD_SPECTRUM
- * @brief
- * 0 - Disable Spread Spectrum function
- * 1 - Enable Spread Spectrum function
- */
-#define SPREAD_SPECTRUM 0
-
-/**
- * @def SB_HPET_TIMER
- * @brief
- * 0 - Disable hpet
- * 1 - Enable hpet
- */
-#define HPET_TIMER 1
-
-/**
- * @def USB_CONFIG
- * @brief bit[0-6] used to control USB
- * 0 - Disable
- * 1 - Enable
- * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0
- * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1
- * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2
- * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3
- * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4
- * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5
- * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6
- */
-#define USB_CONFIG 0x7F
-
-/**
- * @def PCI_CLOCK_CTRL
- * @brief bit[0-4] used for PCI Slots Clock Control,
- * 0 - disable
- * 1 - enable
- * PCI SLOT 0 define at BIT0
- * PCI SLOT 1 define at BIT1
- * PCI SLOT 2 define at BIT2
- * PCI SLOT 3 define at BIT3
- * PCI SLOT 4 define at BIT4
- */
-#define PCI_CLOCK_CTRL 0x1F
-
-/**
- * @def SATA_CONTROLLER
- * @brief INCHIP Sata Controller
- */
-#define SATA_CONTROLLER CIMX_OPTION_ENABLED
-
-/**
- * @def SATA_MODE
- * @brief INCHIP Sata Controller Mode
- * NOTE: DO NOT ALLOW SATA & IDE use same mode
- */
-#define SATA_MODE CONFIG_SB800_SATA_MODE
-
-/**
- * @brief INCHIP Sata IDE Controller Mode
- */
-#define IDE_LEGACY_MODE 0
-#define IDE_NATIVE_MODE 1
-
-/**
- * @def SATA_IDE_MODE
- * @brief INCHIP Sata IDE Controller Mode
- * NOTE: DO NOT ALLOW SATA & IDE use same mode
- */
-#define SATA_IDE_MODE IDE_LEGACY_MODE
-
-/**
- * @def EXTERNAL_CLOCK
- * @brief 00/10: Reference clock from crystal oscillator via
- * PAD_XTALI and PAD_XTALO
- *
- * @def INTERNAL_CLOCK
- * @brief 01/11: Reference clock from internal clock through
- * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
- */
-#define EXTERNAL_CLOCK 0x00
-#define INTERNAL_CLOCK 0x01
-
-/* NOTE: inagua have to using internal clock,
- * otherwise can not detect sata drive
- */
-#define SATA_CLOCK_SOURCE INTERNAL_CLOCK
-
-/**
- * @def SATA_PORT_MULT_CAP_RESERVED
- * @brief 1 ON, 0 0FF
- */
-#define SATA_PORT_MULT_CAP_RESERVED 1
-
-/**
- * @def AZALIA_AUTO
- * @brief Detect Azalia controller automatically.
- *
- * @def AZALIA_DISABLE
- * @brief Disable Azalia controller.
-
- * @def AZALIA_ENABLE
- * @brief Enable Azalia controller.
- */
-#define AZALIA_AUTO 0
-#define AZALIA_DISABLE 1
-#define AZALIA_ENABLE 2
-
-/**
- * @brief INCHIP HDA controller
- */
-#define AZALIA_CONTROLLER AZALIA_AUTO
-
-/**
- * @def AZALIA_PIN_CONFIG
- * @brief
- * 0 - disable
- * 1 - enable
- */
-#define AZALIA_PIN_CONFIG 1
-
-/**
- * @def AZALIA_SDIN_PIN
- * @brief
- * SDIN0 is defined at BIT0 & BIT1
- * 00 - GPIO PIN
- * 01 - Reserved
- * 10 - As a Azalia SDIN pin
- * SDIN1 is defined at BIT2 & BIT3
- * SDIN2 is defined at BIT4 & BIT5
- * SDIN3 is defined at BIT6 & BIT7
- */
-//#define AZALIA_SDIN_PIN 0xAA
-#define AZALIA_SDIN_PIN 0x2A
-
-/**
- * @def GPP_CONTROLLER
- */
-#define GPP_CONTROLLER CIMX_OPTION_ENABLED
-
-/**
- * @def GPP_CFGMODE
- * @brief GPP Link Configuration
- * four possible configuration:
- * GPP_CFGMODE_X4000
- * GPP_CFGMODE_X2200
- * GPP_CFGMODE_X2110
- * GPP_CFGMODE_X1111
- */
-#define GPP_CFGMODE GPP_CFGMODE_X1111
-
-/**
- * @def NB_SB_GEN2
- * 0 - Disable
- * 1 - Enable
- */
-#define NB_SB_GEN2 TRUE
-
-/**
- * @def SB_GPP_GEN2
- * 0 - Disable
- * 1 - Enable
- */
-#define SB_GPP_GEN2 TRUE
-
-/**
- * @def SB_GPP_UNHIDE_PORTS
- * TRUE - ports visible always, even port empty
- * FALSE - ports invisible if port empty
- */
-#define SB_GPP_UNHIDE_PORTS FALSE
-
-/**
- * @def GEC_CONFIG
- * 0 - Enable
- * 1 - Disable
- */
-#define GEC_CONFIG 0
-
-/**
- * @def SIO_HWM_BASE_ADDRESS
- * Super IO HWM base address
- */
-#define SIO_HWM_BASE_ADDRESS 0x290
-
-#endif
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 07:57:05 +0000