mb/asrock: Add Z97E-ITX/ac (Haswell/Broadwell)

This is a rudimentary port of this board. It was done with Haswell
Autoport, wherein some adjustments for Broadwell were made
(Thanks to Angel Pons!).
The VBT was copied from /sys/kernel/debug/dri/1/i915_vbt on version
2.20 of the vendor firmware.

Working:
- Broadwell MRC.bin
- S3 suspend and resume
- All DIMM slots
- Libgfxinit
- HDMI-Out Port
- DVI-I Port (including passive DVI to VGA adapter)
- USB 2.0 Ports
- USB 3.1 Gen1
- RJ-45 LAN Port
- SATA3 6.0 Gb/s Connectors
- m.2 PCIe SSD
- mPCIe WiFi slot
- x16 PCIe slot
- USB 3.1 Gen1 Header
- Front Panel Audio Connector
- edk2

Not yet tested:
- SATA Express 10 Gb/s Connector
- HDMI-In Port
- DisplayPort 1.2
- Optical SPDIF Out Port
- PS/2 Mouse/Keyboard Port
- USB 2.0 Headers

Not working:
- Broadwell CPUs, see commit f5105313cf69 (mb/asrock/z97_extreme6:
Add new mainboard)
Special thanks to Angel Pons for guiding me through the process of
porting this board and pushing it to Gerrit!

Change-Id: I3b940e9281814e8360900221714c0dfa3ae39540
Signed-off-by: Jan Philipp Groß <jeangrande@mailbox.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82760
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>

1 files changed, 21 insertions, 0 deletions

diff --git a/src/mainboard/asrock/z97e-itx_ac/bootblock.c b/src/mainboard/asrock/z97e-itx_ac/bootblock.c
new file mode 100644
index 0000000000..d16fb395a0
--- /dev/null
+++ b/src/mainboard/asrock/z97e-itx_ac/bootblock.c
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/pnp_ops.h>
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct6776/nct6776.h>
+#include <southbridge/intel/lynxpoint/pch.h>
+#define GLOBAL_DEV PNP_DEV(0x2e, 0)
+#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1)
+
+void mainboard_config_superio(void)
+{
+	nuvoton_pnp_enter_conf_state(GLOBAL_DEV);
+	/* Select SIO pin mux states */
+	pnp_write_config(GLOBAL_DEV, 0x1b, 0x48);
+	pnp_write_config(GLOBAL_DEV, 0x24, 0x5c);
+	pnp_write_config(GLOBAL_DEV, 0x27, 0xd0);
+	pnp_write_config(GLOBAL_DEV, 0x2a, 0xe0);
+	pnp_write_config(GLOBAL_DEV, 0x2c, 0x80);
+	pnp_write_config(GLOBAL_DEV, 0x2f, 0x01);
+	nuvoton_pnp_exit_conf_state(GLOBAL_DEV);
+}