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author | Maxim Polyakov <max.senia.poliak@gmail.com> | 2019-06-17 13:31:21 +0300 |
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committer | Felix Held <felix-coreboot@felixheld.de> | 2019-09-01 23:34:12 +0000 |
commit | d947c691bc9bf30ee7276e96b60a727b6bbf06ff (patch) | |
tree | 25495649340c871fc99a3a7076addb4233973bcd /src/mainboard/asrock/h81m-hds/cmos.layout | |
parent | 08aa502d79d04a13c56293021cd66d9c3c270f97 (diff) |
mb/asrock/h110m: rewrite gpio config using macros
This format of PCH GPIOs configuration, unlike the raw DW0 and DW1 [1]
registers values from the inteltool dump, is more understandable and
makes the code much cleaner. The pad configuration in this patch was
generated using the pch-pads-parser utility [2]. The inteltool dump
before and after the patch is identical (see notes)
Notes:
1. For some reason, GPIO RX State (RO) for the GPP_F4 and GPP_G10
changed the value to 0, but this doesn't affect the motherboard
operation. Perhaps this is because PAD_CFG1_GPIO_DRIVER is set to
PAD_CFG_GPI_INT(), and the pad is not actually connected. So far I
haven't circuit diagram to check this out.
2. According to the documentation [1], the value 3h for RXEVCFG is
implemented as setting 0h.
3. If the available macros from gpio_defs.h [3] can't determine the
configuration of the pad, the utility [2] generates common
_PAD_CFG_STRUCT() macros
[1] page 1429,Intel (R) 100 Series and Intel (R) C230 Series PCH
Family Platform Controller Hub (PCH), Datasheet, Vol 2 of 2,
February 2019, Document Number: 332691-003EN
[2] https://github.com/maxpoliak/pch-pads-parser/tree/stable_1.0
[3] src/soc/intel/common/block/include/intelblocks/gpio_defs.h
Change-Id: I01ad4bd29235fbe2b23abce5fbaaa7e63c87f529
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/asrock/h81m-hds/cmos.layout')
0 files changed, 0 insertions, 0 deletions