diff options
author | Subrata Banik <subratabanik@google.com> | 2022-01-03 18:07:13 +0000 |
---|---|---|
committer | Subrata Banik <subratabanik@google.com> | 2022-01-16 13:33:14 +0000 |
commit | a0d9ad322fe603d4d4cbccda9c7edcfbf0b13409 (patch) | |
tree | 669b42cd23e87dd8dd89009173d820057afea520 /src/mainboard/asrock/h77pro4-m | |
parent | 98ce39dce48d9f4b88fb0d71af654f4ed948ea9b (diff) |
soc/intel/skl: Replace dt `HeciEnabled` by `HECI1 disable` config
List of changes:
1. Drop `HeciEnabled` from dt and dt chip configuration.
2. Replace all logic that disables HECI1 based on the `HeciEnabled`
chip config with `DISABLE_HECI1_AT_PRE_BOOT` config.
3. Make dt CSE PCI device `on` by default.
4. Mainboards set DISABLE_HECI1_AT_PRE_BOOT=y to make Heci1
function disable at pre-boot instead of the dt policy that uses
`HeciEnabled = 0`.
Mainboards that choose to make HECI1 enable during boot don't override
`heci1 disable` config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I5c13fe4a78be44403a81c28b1676aecc26c58607
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/asrock/h77pro4-m')
0 files changed, 0 insertions, 0 deletions