Asrock E350M1: Use SPD read code from F14 wrapper

Changes:
 - Get rid of the E350M1 mainboard specific code and use the
   platform generic function wrapper that was added in change
   http://review.coreboot.org/#/c/2497/
   AMD f14: Add SPD read functions to wrapper code

 - Move DIMM addresses into devicetree.cb

 - Add the ASF init that used to be in the SPD read code into
   mainboard_enable()

Notes:
 - The DIMM reads only happen in romstage, so the function is not
   available in ramstage.  Point the read-SPD callback to a generic
   function in ramstage.

Change-Id: I08c2aebc62facc14f94400ee1ad188901ba73f19
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-on: http://review.coreboot.org/2875
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)

1 files changed, 7 insertions, 0 deletions

diff --git a/src/mainboard/asrock/e350m1/devicetree.cb b/src/mainboard/asrock/e350m1/devicetree.cb
index bf358ee295..c908421d0e 100644
--- a/src/mainboard/asrock/e350m1/devicetree.cb
+++ b/src/mainboard/asrock/e350m1/devicetree.cb
@@ -125,6 +125,13 @@ chip northbridge/amd/agesa/family14/root_complex
                         device pci 18.5 on end
                         device pci 18.6 on end
                         device pci 18.7 on end
+
+			register "spdAddrLookup" = "
+			{
+				{ {0xA0, 0xA4}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
+				{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
+			}"
+
                 end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
         end #domain
 end #northbridge/amd/agesa/family14/root_complex