diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-12 19:11:50 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-18 11:48:35 +0000 |
| commit | fa5d0f835b1f3bb8907e616913cbf7b91d09ef26 (patch) | |
| tree | af8d33b500b91fa9e2f1a76d9115086644ccf3d2 /src/mainboard/asrock/b75pro3-m | |
| parent | 59eb2fdb6b06618311ef118996ca8c1d28a85ffc (diff) | |
nb/intel/sandybridge: Set up console in bootblock
Change-Id: Ia041b63201b2a4a2fe6ab11e3497c460f88061d1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/asrock/b75pro3-m')
| -rw-r--r-- | src/mainboard/asrock/b75pro3-m/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/mainboard/asrock/b75pro3-m/early_init.c (renamed from src/mainboard/asrock/b75pro3-m/romstage.c) | 3 |
2 files changed, 4 insertions, 1 deletions
diff --git a/src/mainboard/asrock/b75pro3-m/Makefile.inc b/src/mainboard/asrock/b75pro3-m/Makefile.inc index df00e3749e..598cd90e49 100644 --- a/src/mainboard/asrock/b75pro3-m/Makefile.inc +++ b/src/mainboard/asrock/b75pro3-m/Makefile.inc @@ -17,3 +17,5 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/asrock/b75pro3-m/romstage.c b/src/mainboard/asrock/b75pro3-m/early_init.c index 983de07ff7..296c2de0e7 100644 --- a/src/mainboard/asrock/b75pro3-m/romstage.c +++ b/src/mainboard/asrock/b75pro3-m/early_init.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <bootblock_common.h> #include <device/pci_ops.h> #include <device/pnp_ops.h> #include <northbridge/intel/sandybridge/raminit_native.h> @@ -40,7 +41,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 6 }, }; -void mainboard_config_superio(void) +void bootblock_mainboard_early_init(void) { /* Set GPIOs on superio, enable UART */ nuvoton_pnp_enter_conf_state(SERIAL_DEV); |