Drop GX1, CS5330 and related boards

There is no Cache As Ram for these boards, let's get rid of them.

Change-Id: Ib41f8cd64fc9a440838aea86076d6514aacb301c
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/7117
Reviewed-by: Marc Jones <marc.jones@se-eng.com>

11 files changed, 0 insertions, 403 deletions

diff --git a/src/mainboard/asi/Kconfig b/src/mainboard/asi/Kconfig
deleted file mode 100644
index 29f0895fb0..0000000000
--- a/src/mainboard/asi/Kconfig
+++ /dev/null
@@ -1,38 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-##
-if VENDOR_ASI
-
-choice
-	prompt "Mainboard model"
-
-config BOARD_ASI_MB_5BLGP
-	bool "MB-5BLGP"
-config BOARD_ASI_MB_5BLMP
-	bool "MB-5BLMP"
-
-endchoice
-
-source "src/mainboard/asi/mb_5blgp/Kconfig"
-source "src/mainboard/asi/mb_5blmp/Kconfig"
-
-config MAINBOARD_VENDOR
-	string
-	default "ASI"
-
-endif # VENDOR_ASI
diff --git a/src/mainboard/asi/mb_5blgp/Kconfig b/src/mainboard/asi/mb_5blgp/Kconfig
deleted file mode 100644
index f69f6efafb..0000000000
--- a/src/mainboard/asi/mb_5blgp/Kconfig
+++ /dev/null
@@ -1,45 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-##
-if BOARD_ASI_MB_5BLGP
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-	select CPU_AMD_GEODE_GX1
-	select NORTHBRIDGE_AMD_GX1
-	select SOUTHBRIDGE_AMD_CS5530
-	select SUPERIO_NSC_PC87351
-	select ROMCC
-	select HAVE_PIRQ_TABLE
-	select PIRQ_ROUTE
-	select UDELAY_TSC
-	select BOARD_ROMSIZE_KB_256
-
-config MAINBOARD_DIR
-	string
-	default asi/mb_5blgp
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "MB-5BLGP"
-
-config IRQ_SLOT_COUNT
-	int
-	default 3
-
-endif # BOARD_ASI_MB_5BLGP
diff --git a/src/mainboard/asi/mb_5blgp/board_info.txt b/src/mainboard/asi/mb_5blgp/board_info.txt
deleted file mode 100644
index 0dcbbea5c1..0000000000
--- a/src/mainboard/asi/mb_5blgp/board_info.txt
+++ /dev/null
@@ -1,2 +0,0 @@
-Board name: MB-5BLGP (Neoware Eon 4000s)
-Category: settop
diff --git a/src/mainboard/asi/mb_5blgp/devicetree.cb b/src/mainboard/asi/mb_5blgp/devicetree.cb
deleted file mode 100644
index d84bf0e045..0000000000
--- a/src/mainboard/asi/mb_5blgp/devicetree.cb
+++ /dev/null
@@ -1,55 +0,0 @@
-chip northbridge/amd/gx1		# Northbridge
-  device domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    chip southbridge/amd/cs5530		# Southbridge
-      device pci 0f.0 on end		# Ethernet
-      device pci 12.0 on		# ISA bridge
-        chip superio/nsc/pc87351	# Super I/O
-          device pnp 2e.0 off		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 2e.1 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-          end
-          device pnp 2e.2 on		# COM2
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 2e.e on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 2e.4 on		# System wake-up control (SWC)
-            irq 0x60 = 0x500
-          end
-          device pnp 2e.5 on		# PS/2 mouse
-            irq 0x70 = 12
-          end
-          device pnp 2e.6 on		# PS/2 keyboard
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1
-          end
-          device pnp 2e.7 on		# GPIO
-            irq 0x60 = 0x800
-          end
-          device pnp 2e.8 on		# Fan speed control
-            irq 0x60 = 0x900
-          end
-        end
-      end
-      device pci 12.1 off end		# SMI
-      device pci 12.2 on end		# IDE
-      device pci 12.3 on end		# Audio
-      device pci 12.4 on end		# VGA
-      device pci 13.0 on end		# USB
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "0"	# No connector on this board
-    end
-  end
-  chip cpu/amd/geode_gx1		# CPU
-  end
-end
diff --git a/src/mainboard/asi/mb_5blgp/irq_tables.c b/src/mainboard/asi/mb_5blgp/irq_tables.c
deleted file mode 100644
index b37e8f99d0..0000000000
--- a/src/mainboard/asi/mb_5blgp/irq_tables.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/pirq_routing.h>
-
-static const struct irq_routing_table intel_irq_routing_table = {
-	PIRQ_SIGNATURE,
-	PIRQ_VERSION,
-	32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
-	0x00,			/* Interrupt router bus */
-	(0x12 << 3) | 0x0,	/* Interrupt router device */
-	0x8800,			/* IRQs devoted exclusively to PCI usage */
-	0x1078,			/* Vendor */
-	0x2,			/* Device */
-	0,			/* Miniport data */
-	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
-	0x96,			/* Checksum */
-	{
-		/* bus,        dev | fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
-		{0x00, (0x07 << 3) | 0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0}, /* ISA slot (?) */
-		{0x00, (0x0f << 3) | 0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x2, 0x0}, /* NIC */
-		{0x00, (0x13 << 3) | 0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, /* USB */
-	}
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/asi/mb_5blgp/romstage.c b/src/mainboard/asi/mb_5blgp/romstage.c
deleted file mode 100644
index ac76f34e88..0000000000
--- a/src/mainboard/asi/mb_5blgp/romstage.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <stdint.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <console/console.h>
-#include "northbridge/amd/gx1/raminit.c"
-#include "cpu/x86/bist.h"
-#include "superio/nsc/pc87351/early_serial.c"
-#include "southbridge/amd/cs5530/enable_rom.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, PC87351_SP1)
-
-#include <cpu/intel/romstage.h>
-static void main(unsigned long bist)
-{
-	pc87351_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-	console_init();
-	report_bist_failure(bist);
-	cs5530_enable_rom();
-	sdram_init();
-}
diff --git a/src/mainboard/asi/mb_5blmp/Kconfig b/src/mainboard/asi/mb_5blmp/Kconfig
deleted file mode 100644
index a40c86c328..0000000000
--- a/src/mainboard/asi/mb_5blmp/Kconfig
+++ /dev/null
@@ -1,45 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-##
-if BOARD_ASI_MB_5BLMP
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-	select CPU_AMD_GEODE_GX1
-	select NORTHBRIDGE_AMD_GX1
-	select SOUTHBRIDGE_AMD_CS5530
-	select SUPERIO_NSC_PC87351
-	select ROMCC
-	select HAVE_PIRQ_TABLE
-	select PIRQ_ROUTE
-	select UDELAY_TSC
-	select BOARD_ROMSIZE_KB_256
-
-config MAINBOARD_DIR
-	string
-	default asi/mb_5blmp
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "MB-5BLMP"
-
-config IRQ_SLOT_COUNT
-	int
-	default 5
-
-endif # BOARD_ASI_MB_5BLMP
diff --git a/src/mainboard/asi/mb_5blmp/board_info.txt b/src/mainboard/asi/mb_5blmp/board_info.txt
deleted file mode 100644
index da529cb739..0000000000
--- a/src/mainboard/asi/mb_5blmp/board_info.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-Board name: MB-5BLMP (IGEL WinNET III)
-Category: settop
-Board URL: http://www.hojerteknik.com/winnet.htm
-Flashrom support: y
diff --git a/src/mainboard/asi/mb_5blmp/devicetree.cb b/src/mainboard/asi/mb_5blmp/devicetree.cb
deleted file mode 100644
index e8e6ac3ca5..0000000000
--- a/src/mainboard/asi/mb_5blmp/devicetree.cb
+++ /dev/null
@@ -1,48 +0,0 @@
-chip northbridge/amd/gx1		# Northbridge
-  device domain 0 on
-    device pci 0.0 on end		# Host bridge
-    chip southbridge/amd/cs5530		# Southbridge
-      device pci 0f.0 off end		# Ethernet (Realtek RTL8139B)
-      device pci 12.0 on		# ISA bridge
-        chip superio/nsc/pc87351	# Super I/O
-          device pnp 2e.4 on		# PS/2 keyboard (+ mouse?)
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1
-            # irq 0x72 = 12
-          end
-          device pnp 2e.a on		# PS/2 mouse
-            irq 0x70 = 12
-          end
-          device pnp 2e.e on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 2e.f off		# Floppy
-            io 0x60 = 0x3f2
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 2e.10 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-          end
-          device pnp 2e.12 on		# COM2
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-        end
-      end
-      device pci 12.1 off end		# SMI
-      device pci 12.2 on  end		# IDE
-      device pci 12.3 on  end		# Audio
-      device pci 12.4 on  end		# VGA (onboard)
-      device pci 13.0 on end		# USB
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-    end
-  end
-  chip cpu/amd/geode_gx1		# CPU
-  end
-end
-
diff --git a/src/mainboard/asi/mb_5blmp/irq_tables.c b/src/mainboard/asi/mb_5blmp/irq_tables.c
deleted file mode 100644
index 01d364daea..0000000000
--- a/src/mainboard/asi/mb_5blmp/irq_tables.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/* TODO: This is currently copied from the IEI NOVA-4899R target, but it's
- * quite surely wrong for this board. It gets me further in the boot process
- * than using no irq_tables.c file at all, though!
- */
-
-/* TODO: Add license header. */
-
-#include <arch/pirq_routing.h>
-
-static const struct irq_routing_table intel_irq_routing_table = {
-	PIRQ_SIGNATURE,  /* u32 signature */
-	PIRQ_VERSION,    /* u16 version   */
-	32+16*CONFIG_IRQ_SLOT_COUNT,	 /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
-	0x00,		 /* Where the interrupt router lies (bus) */
-	(0x12<<3)|0x0,   /* Where the interrupt router lies (dev) */
-	0xe00,		 /* IRQs devoted exclusively to PCI usage */
-	0x1078,		 /* Vendor */
-	0x0002,		 /* Device */
-	0,		 /* Miniport data */
-	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
-	0x2d,         /*  u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
-	{
-		/* bus,     dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
-		// USB
-		{0x00,(0x13<<3)|0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
-		// eth0
-		{0x00,(0x0a<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},//0x3, 0x0},
-		// eth1
-		{0x00,(0x0b<<3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x02, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},//0x2, 0x0},
-		// eth2
-		{0x00,(0x0c<<3)|0x0, {{0x04, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},//0x1, 0x0},
-		// PCI slot
-		{0x00,(0x0f<<3)|0x0, {{0x04, 0xdeb8}, {0x03, 0xdeb8}, {0x02, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
-	}
-};
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-        return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/asi/mb_5blmp/romstage.c b/src/mainboard/asi/mb_5blmp/romstage.c
deleted file mode 100644
index 96e884d6dd..0000000000
--- a/src/mainboard/asi/mb_5blmp/romstage.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <console/console.h>
-#include "northbridge/amd/gx1/raminit.c"
-#include "superio/nsc/pc87351/early_serial.c"
-#include "cpu/x86/bist.h"
-#include "southbridge/amd/cs5530/enable_rom.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, PC87351_SP1)
-
-#include <cpu/intel/romstage.h>
-static void main(unsigned long bist)
-{
-	pc87351_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-	console_init();
-	report_bist_failure(bist);
-	cs5530_enable_rom();
-	sdram_init();
-}