diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2017-10-04 23:08:55 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-10-06 15:25:45 +0000 |
| commit | a06f55b8e4a4e51815d654f6125a60c0db3550e4 (patch) | |
| tree | 1722c4aefc423df1e02f11ffc476c139cea3f078 /src/mainboard/artecgroup | |
| parent | 4a8f45f9ad541124688142b186d10b15b9867574 (diff) | |
soc/intel/cannonlake: Enable MRC cache
Enable MRC cache by default.
TEST=Warm reset and check coreboot serial log, MRC related log can be
seen.
Change-Id: I76ece361867737c01cc848c24d8893d43a3d292e
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/artecgroup')
0 files changed, 0 insertions, 0 deletions