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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-07-03 07:50:45 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-07-03 19:23:40 +0000 |
| commit | 5e4a26a76e5ec342e10a5c8ce2ff26eb03bb5bc2 (patch) | |
| tree | 5a88de8787f9600e690c02edb70506041114c546 /src/mainboard/aopen/dxplplusu/bus.h | |
| parent | 810e566c8019f5da2f215bf5a257525ac216dfe5 (diff) | |
aopen/dxplplusu: Replace use of dev_find_slot()
To use fixed PCI bus numbers is always invalid.
Change-Id: Ia2ffdb1f5e0ff398674a016ad4cb94f622c057ff
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/aopen/dxplplusu/bus.h')
| -rw-r--r-- | src/mainboard/aopen/dxplplusu/bus.h | 39 |
1 files changed, 0 insertions, 39 deletions
diff --git a/src/mainboard/aopen/dxplplusu/bus.h b/src/mainboard/aopen/dxplplusu/bus.h deleted file mode 100644 index 12eef12381..0000000000 --- a/src/mainboard/aopen/dxplplusu/bus.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef DXPLPLUSU_BUS_H_INCLUDED -#define DXPLPLUSU_BUS_H_INCLUDED - -/* These were determined by seeing how coreboot enumerates the various - * PCI (and PCI-like) buses on the board. - */ - -#define PCI_BUS_ROOT 0 -#define PCI_BUS_AGP 1 /* AGP */ -#define PCI_BUS_E7501_HI_B 2 /* P64H2#1 */ -#define PCI_BUS_P64H2_B 3 /* P64H2#1 bus B */ -#define PCI_BUS_P64H2_A 4 /* P64H2#1 bus A */ -#define PCI_BUS_ICH4 5 /* ICH4 */ - -/* IOAPIC addresses determined by coreboot enumeration. */ -/* Someday add functions to get APIC IDs and versions from the chips themselves. */ - -#define IOAPIC_ICH4 2 -#define IOAPIC_P64H2_BUS_B 3 /* IOAPIC 3 at 02:1c.0 MBAR = fe300000 DataAddr = fe300010 */ -#define IOAPIC_P64H2_BUS_A 4 /* IOAPIC 4 at 02:1e.0 MBAR = fe301000 DataAddr = fe301010 */ - -#define INTEL_IOAPIC_NUM_INTERRUPTS 24 /* Both ICH-4 and P64-H2 */ - -#endif |