diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2011-11-03 15:22:01 +0200 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2012-03-08 14:26:24 +0100 |
| commit | 91162705a65e87c56d9fc58edfe597140d1b4d53 (patch) | |
| tree | e549c88e3aa264f3817ae4efc7e0a2ca72394cf9 /src/mainboard/aopen/dxplplusu/Kconfig | |
| parent | c5fc7db3559e080858461b724251f87be6faa2cd (diff) | |
Add support for A-Open DXPL Plus-U motherboard
This is an old (pre-2005) entry-level server mainboard. The code
is adapted from mainboard/intel/xe7501devkit.
Featured chips:
- Dual socket604
- E7505 northbridge
- 82801DB southbridge (with EHCI debug port)
- 82870p2 PCI-X bridge
- LPC47M102S-MC super-io
- 512kB FWH flash (flashrom does the job well)
What works:
- Dual-Xeon P4/HT boot with microcode update
- RAM: registered ECC DDR266 in dual-channel
- PCI-X slot interrupts with ACPI and I/O apic
- On-board PCI-X GbE and SCSI
- ACPI power-off and wakeup with PME#
Notes :
- Current ACPI is more or less a mess
- Interrupts do not route correctly with PIRQ
- MP-table is not implemented
- Issues with reboots remain (cold and warm)
- Many superio devices are disabled by default
- Audio codec is not investigated
Change-Id: I02d18c83f485a09ada65dde03bcc86e9163f2011
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/303
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/mainboard/aopen/dxplplusu/Kconfig')
| -rw-r--r-- | src/mainboard/aopen/dxplplusu/Kconfig | 63 |
1 files changed, 63 insertions, 0 deletions
diff --git a/src/mainboard/aopen/dxplplusu/Kconfig b/src/mainboard/aopen/dxplplusu/Kconfig new file mode 100644 index 0000000000..c3025d157a --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/Kconfig @@ -0,0 +1,63 @@ +if BOARD_AOPEN_DXPLPLUSU + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_MPGA604 + select NORTHBRIDGE_INTEL_E7505 + select SOUTHBRIDGE_INTEL_I82870 + select SOUTHBRIDGE_INTEL_I82801DX + select SUPERIO_SMSC_LPC47M10X + select ROMCC + select HAVE_HARD_RESET +# select HAVE_PIRQ_TABLE +# select PIRQ_ROUTE + select UDELAY_TSC + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_512 + +config MAINBOARD_DIR + string + default aopen/dxplplusu + +config MAINBOARD_PART_NUMBER + string + default "DXPL Plus-U" + +config DCACHE_RAM_BASE + hex + default 0xcf000 + +config DCACHE_RAM_SIZE + hex + default 0x1000 + +config IRQ_SLOT_COUNT + int + default 12 + +config BOARD_HAS_FADT + bool + default y + +config LOGICAL_CPUS + bool + default n + +config MAX_CPUS + int + default 4 + +config MAX_PHYSICAL_CPUS + int + default 2 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x0 + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x0 + +endif # BOARD_AOPEN_DXPLPLUSU |