mb/aoostar: Add Alder Lake based AOOSTAR R1 (WTR_R1)

AOOSTAR R1 is a Chinese NAS based on Intel N100 (Alder Lake N), with
two 3.5" HDD slots, an M.2 NVMe 2280 SSD slot and a single DDR4-3200
SODIMM slot up to 32GB. It also comes with 2x 2.5Gb Intel NICs,
Intel AX200 WiFi + BT and USB-C Alt-DP Power Delivery.

Working:
- DDR4 RAM (tested with Crucial 16GB 3200MHz CL22)
- Automatic FAN control (IT8613E Super I/O)
- M.2 NVME slot
- 2x SATA ports (Issue on 3.5" HDD, see below)
- USB 2.0 ports
- USB 3.0 ports
- USB-C port with Alt-DP and PD
- HDMI / DisplayPort ports
- 2x 2.5Gb NICs
- WiFi + BT
- MicroSD card reader
- ASPM (Unavailable on stock)
- Linux (Arch Linux, kernel 6.8.7-arch1-1) UEFI booting with EDK2
- Windows 10 UEFI booting with EDK2

Broken:
- Power button (OFF->ON broken, ON->OFF works)
- 3.5" SATA HDDs (Detected only after reboot)

Untested:
- Internal audio
- S3

My motivation for doing this port is enabling ASPM, as it makes a
great difference on idle power consumption (from 8.4W to 5W measured
from the wall).

The last remaining annoyance of this port is the power button not
working. I spent a few hours double checking the Super I/O registers but
then I gave up. A workaround for this is to use the "ON after power
loss" feature and reconnect the power cord to turn on the board.
It's not a big problem for a NAS that will stay ON 24/7.
Any hint on the power button or 3.5" HDD issue is welcome.

VBT extracted from vendor UEFI firmware version 1AXFE 0.01 x64
(Build date and time 11/29/2023 10:57:44)
Compiled with FSP GOP video initialization, using IFD descriptor
and ME blob extracted from vendor UEFI firmware (see above).

The board can be flashed externally using a 1.8V adapter, I used a
CH341a modded for 3.3V I/O. Internal flashing works, as flash is
not read/write protected.

Patchset 5: Re-enabled dptf, added default options to Kconfig.
Patchset 7: Configured USB port mapping and overcurrent, USB3.0 works
Patchset 8: Fixed microSD card reader
Patchset 13: Change Super I/O Fan configuration to reduce fan noise

Change-Id: I9414eb742b6b90459e010b038c1994537e9801a5
Signed-off-by: Federico Amedeo Izzo <federico@izzo.pro>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82010
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 26 insertions, 0 deletions

diff --git a/src/mainboard/aoostar/wtr_r1/bootblock.c b/src/mainboard/aoostar/wtr_r1/bootblock.c
new file mode 100644
index 0000000000..d494f9ad17
--- /dev/null
+++ b/src/mainboard/aoostar/wtr_r1/bootblock.c
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8613e/it8613e.h>
+
+#define GPIO_DEV PNP_DEV(0x2e, IT8613E_GPIO)
+
+void bootblock_mainboard_early_init(void)
+{
+	/* Set up GPIOs on Super I/O. */
+	ite_reg_write(GPIO_DEV, 0x25, 0x01); // Enable Pin GP10
+	ite_reg_write(GPIO_DEV, 0x27, 0x02); // Enable Pin GP31
+	ite_reg_write(GPIO_DEV, 0x28, 0x01); // Enable Pin GP40
+	ite_reg_write(GPIO_DEV, 0x29, 0x01); // Enable Pin GP50
+	ite_reg_write(GPIO_DEV, 0x2c, 0x41); // Internal Voltage Divider for ACC3
+	ite_reg_write(GPIO_DEV, 0xbc, 0xc0); // GP56, GP57 Internal pullup
+	ite_reg_write(GPIO_DEV, 0xbd, 0x03); // GP60, GP61 Internal pullup
+	ite_reg_write(GPIO_DEV, 0xc3, 0x41); // GP40, GP46 Simple I/O function
+	ite_set_3vsbsw(GPIO_DEV, true);
+	ite_delay_pwrgd3(GPIO_DEV);
+}
+
+void bootblock_mainboard_init(void)
+{
+}