mb/amd/south_station: Convert to ASL 2.0 syntax

Generated 'build/dsdt.dsl' files are identical.

Change-Id: I52c33679fbb7e9807423fc0fcc470e54105013db
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46151
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

5 files changed, 130 insertions, 134 deletions

diff --git a/src/mainboard/amd/south_station/acpi/ide.asl b/src/mainboard/amd/south_station/acpi/ide.asl
index 663b36af63..e3a1bec04e 100644
--- a/src/mainboard/amd/south_station/acpi/ide.asl
+++ b/src/mainboard/amd/south_station/acpi/ide.asl
@@ -50,11 +50,11 @@ OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
 
 Method(GTTM, 1) /* get total time*/
 {
-	Store(And(Arg0, 0x0F), Local0)	/* Recovery Width */
-	Increment(Local0)
-	Store(ShiftRight(Arg0, 4), Local1)	/* Command Width */
-	Increment(Local1)
-	Return(Multiply(30, Add(Local0, Local1)))
+	Local0 = Arg0 & 0x0F	/* Recovery Width */
+	Local0++
+	Local1 = Arg0 >> 4	/* Command Width */
+	Local1++
+	Return(30 * (Local0 + Local1))
 }
 
 Device(PRID)
@@ -76,30 +76,30 @@ Device(PRID)
 		CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
 
 		/* Just return if the channel is disabled */
-		If(And(PPCR, 0x01)) { /* primary PIO control */
+		If (PPCR & 0x01) { /* primary PIO control */
 			Return(OTBF)
 		}
 
 		/* Always tell them independent timing available and IOChannelReady used on both drives */
-		Or(BFFG, 0x1A, BFFG)
+		BFFG |= 0x1A
 
-		Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming  to PIO spd0 */
-		Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing  to PIO spd1 */
+		PSD0 = GTTM (PPTM) /* save total time of primary PIO master timing  to PIO spd0 */
+		PSD1 = GTTM (PPTS) /* save total time of primary PIO slave Timing  to PIO spd1 */
 
-		If(And(PDCR, 0x01)) {	/* It's under UDMA mode */
-			Or(BFFG, 0x01, BFFG)
-			Store(DerefOf(Index(UDTT, PDMM)), DSD0)
+		If (PDCR & 0x01) {	/* It's under UDMA mode */
+			BFFG |= 0x01
+			DSD0 = DerefOf(UDTT [PDMM])
 		}
 		Else {
-			Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing,  DmaSpd0 */
+			DSD0 = GTTM (PMTM) /* Primary MWDMA Master Timing,  DmaSpd0 */
 		}
 
-		If(And(PDCR, 0x02)) {	/* It's under UDMA mode */
-			Or(BFFG, 0x04, BFFG)
-			Store(DerefOf(Index(UDTT, PDSM)), DSD1)
+		If (PDCR & 0x02) {	/* It's under UDMA mode */
+			BFFG |= 0x04
+			DSD1 = DerefOf(UDTT [PDSM])
 		}
 		Else {
-			Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing,  DmaSpd0 */
+			DSD1 = GTTM (PMTS) /* Primary MWDMA Slave Timing,  DmaSpd0 */
 		}
 
 		Return(OTBF) /* out buffer */
@@ -120,35 +120,35 @@ Device(PRID)
 		CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
 		CreateDwordField(INBF, 16, BFFG) /*buffer flag */
 
-		Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
-		Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
-		Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
-		Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
+		Local0 = Match (POTT, MLE, PSD0, MTR, 0, 0)
+		PPMM = Local0 % 5 /* Primary PIO master Mode */
+		Local1 = Match (POTT, MLE, PSD1, MTR, 0, 0)
+		PPSM = Local1 % 5 /* Primary PIO slave Mode */
 
-		Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
-		Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
+		PPTM = DerefOf(PORT [Local0]) /* Primary PIO Master Timing */
+		PPTS = DerefOf(PORT [Local1]) /* Primary PIO Slave Timing */
 
-		If(And(BFFG, 0x01)) {	/* Drive 0 is under UDMA mode */
-			Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
-			Divide(Local0, 7, PDMM,)
-			Or(PDCR, 0x01, PDCR)
+		If (BFFG & 0x01) {	/* Drive 0 is under UDMA mode */
+			Local0 = Match (UDTT, MLE, DSD0, MTR, 0, 0)
+			PDMM = Local0 % 7
+			PDCR |= 0x01
 		}
 		Else {
-			If(LNotEqual(DSD0, 0xFFFFFFFF)) {
-				Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
-				Store(DerefOf(Index(MDRT, Local0)), PMTM)
+			If (DSD0 != 0xFFFFFFFF) {
+				Local0 = Match (MDTT, MLE, DSD0, MTR, 0, 0)
+				PMTM = DerefOf(MDRT [Local0])
 			}
 		}
 
-		If(And(BFFG, 0x04)) {	/* Drive 1 is under UDMA mode */
-			Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
-			Divide(Local0, 7, PDSM,)
-			Or(PDCR, 0x02, PDCR)
+		If (BFFG & 0x04) {	/* Drive 1 is under UDMA mode */
+			Local0 = Match (UDTT, MLE, DSD1, MTR, 0, 0)
+			PDSM = Local0 % 7
+			PDCR |= 0x02
 		}
 		Else {
-			If(LNotEqual(DSD1, 0xFFFFFFFF)) {
-				Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
-				Store(DerefOf(Index(MDRT, Local0)), PMTS)
+			If (DSD1 != 0xFFFFFFFF) {
+				Local0 = Match (MDTT, MLE, DSD1, MTR, 0, 0)
+				PMTS = DerefOf(MDRT [Local0])
 			}
 		}
 		/* Return(INBF) */
@@ -168,21 +168,19 @@ Device(PRID)
 			CreateByteField(CMBF, 12, CMDB)
 			CreateByteField(CMBF, 19, CMDC)
 
-			Store(0xA0, CMDA)
-			Store(0xA0, CMDB)
-			Store(0xA0, CMDC)
+			CMDA = 0xA0
+			CMDB = 0xA0
+			CMDC = 0xA0
 
-			Or(PPMM, 0x08, POMD)
+			POMD = PPMM | 0x08
 
-			If(And(PDCR, 0x01)) {
-				Or(PDMM, 0x40, DMMD)
+			If (PDCR & 0x01) {
+				DMMD = PDMM | 0x40
 			}
 			Else {
-				Store(Match
-				      (MDTT, MLE, GTTM(PMTM),
-				       MTR, 0, 0), Local0)
-				If(LLess(Local0, 3)) {
-					Or(0x20, Local0, DMMD)
+				Local0 = Match (MDTT, MLE, GTTM(PMTM), MTR, 0, 0)
+				If (Local0 < 3) {
+					DMMD = Local0 | 0x20
 				}
 			}
 			Return(CMBF)
@@ -204,21 +202,19 @@ Device(PRID)
 			CreateByteField(CMBF, 12, CMDB)
 			CreateByteField(CMBF, 19, CMDC)
 
-			Store(0xB0, CMDA)
-			Store(0xB0, CMDB)
-			Store(0xB0, CMDC)
+			CMDA = 0xB0
+			CMDB = 0xB0
+			CMDC = 0xB0
 
-			Or(PPSM, 0x08, POMD)
+			POMD = PPSM | 0x08
 
-			If(And(PDCR, 0x02)) {
-				Or(PDSM, 0x40, DMMD)
+			If (PDCR & 0x02) {
+				DMMD = PDSM | 0x40
 			}
 			Else {
-				Store(Match
-				      (MDTT, MLE, GTTM(PMTS),
-				       MTR, 0, 0), Local0)
-				If(LLess(Local0, 3)) {
-					Or(0x20, Local0, DMMD)
+				Local0 = Match (MDTT, MLE, GTTM(PMTS), MTR, 0, 0)
+				If (Local0 < 3) {
+					DMMD = Local0 | 0x20
 				}
 			}
 			Return(CMBF)
diff --git a/src/mainboard/amd/south_station/acpi/mainboard.asl b/src/mainboard/amd/south_station/acpi/mainboard.asl
index e4a0c799fe..a1eb03b469 100644
--- a/src/mainboard/amd/south_station/acpi/mainboard.asl
+++ b/src/mainboard/amd/south_station/acpi/mainboard.asl
@@ -18,20 +18,20 @@ Name(PICM, One)	/* Assume APIC */
 Scope(\_SB) {
 	Method(OSFL, 0){
 
-		if(LNotEqual(OSVR, Ones)) {Return(OSVR)}	/* OS version was already detected */
+		if (OSVR != Ones) {Return (OSVR)}	/* OS version was already detected */
 
 		if(CondRefOf(\_OSI))
 		{
-			Store(1, OSVR)					/* Assume some form of XP */
+			OSVR = 1				/* Assume some form of XP */
 			if (\_OSI("Windows 2006"))		/* Vista */
 			{
-				Store(2, OSVR)
+				OSVR = 2
 			}
 		} else {
-			If(WCMP(\_OS,"Linux")) {
-				Store(3, OSVR)				/* Linux */
+			If (WCMP(\_OS,"Linux")) {
+				OSVR = 3			/* Linux */
 			} Else {
-				Store(4, OSVR)				/* Gotta be WinCE */
+				OSVR = 4			/* Gotta be WinCE */
 			}
 		}
 		Return(OSVR)
diff --git a/src/mainboard/amd/south_station/acpi/sata.asl b/src/mainboard/amd/south_station/acpi/sata.asl
index 9344ff1714..e924b571cd 100644
--- a/src/mainboard/amd/south_station/acpi/sata.asl
+++ b/src/mainboard/amd/south_station/acpi/sata.asl
@@ -35,7 +35,7 @@ Device(PMRY)
 	Device(PMST) {
 		Name(_ADR, 0)
 		Method(_STA,0) {
-			if (LGreater(P0IS,0)) {
+			if (P0IS > 0) {
 				return (0x0F) /* sata is visible */
 			}
 			else {
@@ -48,7 +48,7 @@ Device(PMRY)
 	{
 		Name(_ADR, 1)
 		Method(_STA,0) {
-			if (LGreater(P1IS,0)) {
+			if (P1IS > 0) {
 				return (0x0F) /* sata is visible */
 			}
 			else {
@@ -70,7 +70,7 @@ Device(SEDY)
 	{
 		Name(_ADR, 0)
 		Method(_STA,0) {
-			if (LGreater(P2IS,0)) {
+			if (P2IS > 0) {
 				return (0x0F) /* sata is visible */
 			}
 			else {
@@ -83,7 +83,7 @@ Device(SEDY)
 	{
 		Name(_ADR, 1)
 		Method(_STA,0) {
-			if (LGreater(P3IS,0)) {
+			if (P3IS > 0) {
 				return (0x0F) /* sata is visible */
 			}
 			else {
@@ -97,35 +97,35 @@ Device(SEDY)
 Scope(\_GPE) {
 	Method(_L1F,0x0,NotSerialized) {
 		if (\_SB.P0PR) {
-			if (LGreater(\_SB.P0IS,0)) {
+			if (\_SB.P0IS > 0) {
 				sleep(32)
 			}
 			Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			store(one, \_SB.P0PR)
+			 \_SB.P0PR = 1
 		}
 
 		if (\_SB.P1PR) {
-			if (LGreater(\_SB.P1IS,0)) {
+			if (\_SB.P1IS > 0) {
 				sleep(32)
 			}
 			Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			store(one, \_SB.P1PR)
+			\_SB.P1PR = 1
 		}
 
 		if (\_SB.P2PR) {
-			if (LGreater(\_SB.P2IS,0)) {
+			if (\_SB.P2IS > 0) {
 				sleep(32)
 			}
 			Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			store(one, \_SB.P2PR)
+			\_SB.P2PR = 1
 		}
 
 		if (\_SB.P3PR) {
-			if (LGreater(\_SB.P3IS,0)) {
+			if (\_SB.P3IS > 0) {
 				sleep(32)
 			}
 			Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			store(one, \_SB.P3PR)
+			\_SB.P3PR = 1
 		}
 	}
 }
diff --git a/src/mainboard/amd/south_station/acpi/sleep.asl b/src/mainboard/amd/south_station/acpi/sleep.asl
index 76b5f9edc6..3b6fd02055 100644
--- a/src/mainboard/amd/south_station/acpi/sleep.asl
+++ b/src/mainboard/amd/south_station/acpi/sleep.asl
@@ -26,23 +26,23 @@ Method(\_PTS, 1) {
 	/* DBGO("\n") */
 
 	/* Don't allow PCIRST# to reset USB */
-	if (LEqual(Arg0,3)){
-		Store(0,URRE)
+	if (Arg0 == 3){
+		URRE = 0
 	}
 
 	/* Clear sleep SMI status flag and enable sleep SMI trap. */
-	/*Store(One, CSSM)
-	Store(One, SSEN)*/
+	/*CSSM = 1
+	SSEN = 1*/
 
 	/* On older chips, clear PciExpWakeDisEn */
-	/*if (LLessEqual(\_SB.SBRI, 0x13)) {
-	*	Store(0,\_SB.PWDE)
+	/*if (\_SB.SBRI <= 0x13) {
+	*	\_SB.PWDE = 0
 	*}
 	*/
 
 	/* Clear wake status structure. */
-	Store(0, Index(WKST,0))
-	Store(0, Index(WKST,1))
+	WKST [0] = 0
+	WKST [1] = 0
 } /* End Method(\_PTS) */
 
 /*
@@ -67,21 +67,21 @@ Method(\_WAK, 1) {
 	/* DBGO(" to S0\n") */
 
 	/* Re-enable HPET */
-	Store(1,HPDE)
+	HPDE = 1
 
 	/* Restore PCIRST# so it resets USB */
-	if (LEqual(Arg0,3)){
-		Store(1,URRE)
+	if (Arg0 == 3){
+		URRE = 1
 	}
 
 	/* Arbitrarily clear PciExpWakeStatus */
-	Store(PWST, Local1)
-	Store(Local1, PWST)
+	Local1 = PWST
+	PWST = Local1
 
-	/* if (DeRefOf(Index(WKST,0))) {
-	*	Store(0, Index(WKST,1))
+	/* if (DeRefOf(WKST [0])) {
+	*	WKST [1] = 0
 	* } else {
-	*	Store(Arg0, Index(WKST,1))
+	*	WKST [1] = Arg0
 	* }
 	*/
 	Return(WKST)
diff --git a/src/mainboard/amd/south_station/acpi/usb_oc.asl b/src/mainboard/amd/south_station/acpi/usb_oc.asl
index 4ecc52ade9..e4ed275617 100644
--- a/src/mainboard/amd/south_station/acpi/usb_oc.asl
+++ b/src/mainboard/amd/south_station/acpi/usb_oc.asl
@@ -14,134 +14,134 @@ Name(UOM9, 6)
 
 Method(UCOC, 0) {
 	Sleep(20)
-	Store(0x13,CMTI)
-	Store(0,GPSL)
+	CMTI = 0x13
+	GPSL = 0
 }
 
 /* USB Port 0 overcurrent uses Gpm 0 */
-If(LLessEqual(UOM0,9)) {
+If (UOM0 <= 9) {
 	Scope (\_GPE) {
 		Method (_L13) {
 			UCOC()
-			if(LEqual(GPB0,PLC0)) {
-				Not(PLC0,PLC0)
-				Store(PLC0, \_SB.PT0D)
+			if (GPB0 == PLC0) {
+				PLC0 = ~PLC0
+				\_SB.PT0D = PLC0
 			}
 		}
 	}
 }
 
 /* USB Port 1 overcurrent uses Gpm 1 */
-If (LLessEqual(UOM1,9)) {
+If (UOM1 <= 9) {
 	Scope (\_GPE) {
 		Method (_L14) {
 			UCOC()
-			if (LEqual(GPB1,PLC1)) {
-				Not(PLC1,PLC1)
-				Store(PLC1, \_SB.PT1D)
+			if (GPB1 == PLC1) {
+				PLC1 = ~PLC1
+				\_SB.PT1D = PLC1
 			}
 		}
 	}
 }
 
 /* USB Port 2 overcurrent uses Gpm 2 */
-If (LLessEqual(UOM2,9)) {
+If (UOM2 <= 9) {
 	Scope (\_GPE) {
 		Method (_L15) {
 			UCOC()
-			if (LEqual(GPB2,PLC2)) {
-				Not(PLC2,PLC2)
-				Store(PLC2, \_SB.PT2D)
+			if (GPB2 == PLC2) {
+				PLC2 = ~PLC2
+				\_SB.PT2D = PLC2
 			}
 		}
 	}
 }
 
 /* USB Port 3 overcurrent uses Gpm 3 */
-If (LLessEqual(UOM3,9)) {
+If (UOM3 <= 9) {
 	Scope (\_GPE) {
 		Method (_L16) {
 			UCOC()
-			if (LEqual(GPB3,PLC3)) {
-				Not(PLC3,PLC3)
-				Store(PLC3, \_SB.PT3D)
+			if (GPB3 == PLC3) {
+				PLC3 = ~PLC3
+				\_SB.PT3D = PLC3
 			}
 		}
 	}
 }
 
 /* USB Port 4 overcurrent uses Gpm 4 */
-If (LLessEqual(UOM4,9)) {
+If (UOM4 <= 9) {
 	Scope (\_GPE) {
 		Method (_L19) {
 			UCOC()
-			if (LEqual(GPB4,PLC4)) {
-				Not(PLC4,PLC4)
-				Store(PLC4, \_SB.PT4D)
+			if (GPB4 == PLC4) {
+				PLC4 = ~PLC4
+				\_SB.PT4D = PLC4
 			}
 		}
 	}
 }
 
 /* USB Port 5 overcurrent uses Gpm 5 */
-If (LLessEqual(UOM5,9)) {
+If (UOM5 <= 9) {
 	Scope (\_GPE) {
 		Method (_L1A) {
 			UCOC()
-			if (LEqual(GPB5,PLC5)) {
-				Not(PLC5,PLC5)
-				Store(PLC5, \_SB.PT5D)
+			if (GPB5 == PLC5) {
+				PLC5 = ~PLC5
+				\_SB.PT5D = PLC5
 			}
 		}
 	}
 }
 
 /* USB Port 6 overcurrent uses Gpm 6 */
-If (LLessEqual(UOM6,9)) {
+If (UOM6 <= 9) {
 	Scope (\_GPE) {
 		/* Method (_L1C) { */
 		Method (_L06) {
 			UCOC()
-			if (LEqual(GPB6,PLC6)) {
-				Not(PLC6,PLC6)
-				Store(PLC6, \_SB.PT6D)
+			if (GPB6 == PLC6) {
+				PLC6 = ~PLC6
+				\_SB.PT6D = PLC6
 			}
 		}
 	}
 }
 
 /* USB Port 7 overcurrent uses Gpm 7 */
-If (LLessEqual(UOM7,9)) {
+If (UOM7 <= 9) {
 	Scope (\_GPE) {
 		/* Method (_L1D) { */
 		Method (_L07) {
 			UCOC()
-			if (LEqual(GPB7,PLC7)) {
-				Not(PLC7,PLC7)
-				Store(PLC7, \_SB.PT7D)
+			if (GPB7 == PLC7) {
+				PLC7 = ~PLC7
+				\_SB.PT7D = PLC7
 			}
 		}
 	}
 }
 
 /* USB Port 8 overcurrent uses Gpm 8 */
-If (LLessEqual(UOM8,9)) {
+If (UOM8 <= 9) {
 	Scope (\_GPE) {
 		Method (_L17) {
-			if (LEqual(G8IS,PLC8)) {
-				Not(PLC8,PLC8)
-				Store(PLC8, \_SB.PT8D)
+			if (G8IS == PLC8) {
+				PLC8 = ~PLC8
+				\_SB.PT8D = PLC8
 			}
 		}
 	}
 }
 
 /* USB Port 9 overcurrent uses Gpm 9 */
-If (LLessEqual(UOM9,9)) {
+If (UOM9 <= 9) {
 	Scope (\_GPE) {
 		Method (_L0E) {
-			if (LEqual(G9IS,0)) {
-			Store(1,\_SB.PT9D)
+			if (G9IS == 0) {
+			\_SB.PT9D = 1
 			}
 		}
 	}