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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-03-04 07:50:38 +0200 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-08-24 10:31:18 +0000 |
commit | 46379c74ad829863a616e0d35aeea9c7fd344c33 (patch) | |
tree | a938d95bc2f733b1ae2d11865e01c3086ef2149e /src/mainboard/amd/parmer/romstage.c | |
parent | 65200be7fe6aba9f9a9b8f9e00fcab12fdca5ccd (diff) |
amd/parmer: Switch away from AGESA_LEGACY
Change-Id: I3730bf87030b7e20991e1de00d2024e4b02f4c19
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/amd/parmer/romstage.c')
-rw-r--r-- | src/mainboard/amd/parmer/romstage.c | 77 |
1 files changed, 5 insertions, 72 deletions
diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index 70747044f4..1736d48bc2 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -13,84 +13,17 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/acpi.h> #include <arch/io.h> -#include <arch/stages.h> -#include <device/pnp_def.h> #include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <commonlib/loglevel.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesa_helper.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> +#include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/agesa/hudson/hudson.h> -#include <cpu/amd/agesa/s3_resume.h> -#include "cbmem.h" - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - /* Set LPC decode enables. */ - pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - pci_write_config32(dev, 0x44, 0xff03ffd5); - hudson_lpc_port80(); - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - - post_code(0x31); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - post_code(0x39); - - agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - post_code(0x41); - agesawrapper_amdinitenv(); - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - amd_initcpuio(); - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - - post_code(0x50); - copy_and_run(); + pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - post_code(0x54); /* Should never see this post code. */ + /* For serial port option, plug-in card on LPC. */ + pci_write_config32(dev, 0x44, 0xff03ffd5); } |