diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-12-07 23:19:35 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-12-12 18:30:55 +0000 |
| commit | 5aaaee3486b9f5c1fe4b1396de94e2604ebfd766 (patch) | |
| tree | ea1465949f48323bc32ce7f1882b4a3bbc93fc13 /src/mainboard/amd/onyx/devicetree.cb | |
| parent | 2f58bbd686088597aa33f1b44450957443cd8714 (diff) | |
soc/amd/genoa/chipset.cb: disable IOMMU devices by default
Disable the IOMMU PCI devices in the chipset devicetree. In order for
the IOMMU devices on the Onyx mainboard still be enabled, enable them in
the mainboard devicetree.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8c1bbbf370a3b5566a8484bcfa88dc4efa31222b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79409
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/amd/onyx/devicetree.cb')
| -rw-r--r-- | src/mainboard/amd/onyx/devicetree.cb | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/amd/onyx/devicetree.cb b/src/mainboard/amd/onyx/devicetree.cb index 3d63da586b..80c25e1899 100644 --- a/src/mainboard/amd/onyx/devicetree.cb +++ b/src/mainboard/amd/onyx/devicetree.cb @@ -53,6 +53,7 @@ chip soc/amd/genoa }" device domain 0 on + device ref iommu_0 on end device ref gpp_bridge_0_0_a on chip vendorcode/amd/opensil/genoa_poc/mpio # P2 register "start_lane" = "48" @@ -84,6 +85,7 @@ chip soc/amd/genoa end device domain 1 on + device ref iommu_1 on end device ref gpp_bridge_1_0_a on chip vendorcode/amd/opensil/genoa_poc/mpio # P3 register "start_lane" = "16" @@ -105,6 +107,7 @@ chip soc/amd/genoa end device domain 2 on + device ref iommu_2 on end device ref gpp_bridge_2_0_a on chip vendorcode/amd/opensil/genoa_poc/mpio # P1 register "start_lane" = "32" @@ -128,6 +131,7 @@ chip soc/amd/genoa end device domain 3 on + device ref iommu_3 on end device ref gpp_bridge_3_0_a on chip vendorcode/amd/opensil/genoa_poc/mpio # P0 register "start_lane" = "0" |