From 5aaaee3486b9f5c1fe4b1396de94e2604ebfd766 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Thu, 7 Dec 2023 23:19:35 +0100 Subject: soc/amd/genoa/chipset.cb: disable IOMMU devices by default Disable the IOMMU PCI devices in the chipset devicetree. In order for the IOMMU devices on the Onyx mainboard still be enabled, enable them in the mainboard devicetree. Signed-off-by: Felix Held Change-Id: I8c1bbbf370a3b5566a8484bcfa88dc4efa31222b Reviewed-on: https://review.coreboot.org/c/coreboot/+/79409 Reviewed-by: Varshit Pandya Reviewed-by: Matt DeVillier Tested-by: build bot (Jenkins) --- src/mainboard/amd/onyx/devicetree.cb | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/mainboard/amd/onyx/devicetree.cb') diff --git a/src/mainboard/amd/onyx/devicetree.cb b/src/mainboard/amd/onyx/devicetree.cb index 3d63da586b..80c25e1899 100644 --- a/src/mainboard/amd/onyx/devicetree.cb +++ b/src/mainboard/amd/onyx/devicetree.cb @@ -53,6 +53,7 @@ chip soc/amd/genoa }" device domain 0 on + device ref iommu_0 on end device ref gpp_bridge_0_0_a on chip vendorcode/amd/opensil/genoa_poc/mpio # P2 register "start_lane" = "48" @@ -84,6 +85,7 @@ chip soc/amd/genoa end device domain 1 on + device ref iommu_1 on end device ref gpp_bridge_1_0_a on chip vendorcode/amd/opensil/genoa_poc/mpio # P3 register "start_lane" = "16" @@ -105,6 +107,7 @@ chip soc/amd/genoa end device domain 2 on + device ref iommu_2 on end device ref gpp_bridge_2_0_a on chip vendorcode/amd/opensil/genoa_poc/mpio # P1 register "start_lane" = "32" @@ -128,6 +131,7 @@ chip soc/amd/genoa end device domain 3 on + device ref iommu_3 on end device ref gpp_bridge_3_0_a on chip vendorcode/amd/opensil/genoa_poc/mpio # P0 register "start_lane" = "0" -- cgit v1.2.3