mainboard: Add AMD DB-FT3b (Olive Hill+) with Steppe Eagle SoC

Create a new mainboard based on the AMD DB-FT3 development board
(Olive Hill) using an AMD Steppe Eagle processor.  The actual DB-FT3
and DB-FT3b mainboards are identical except for the soldered-down
SoC device.  The new AMD DB-FT3b development board (Olive Hill+)
features:

	* Mini-ITX form factor
	* 2x DisplayPort
	* 1x VGA
	* Integrated Realtek RTL8111-compatible Ethernet
	* 2x USB 3.0 ports
	* 2x USB 2.0 externally-accessible ports
	* 2x USB 2.0 internally-accessible ports (via headers)
	* micro LPC header
	* Integrated platform security processor
	* 2x Full-size DDR3 DIMM support (1 channel)
	* Realtek ALC272 HD audio
	* 2x SATA ports
	* 1x SD card slot
	* 1x PCIe (x4) slot
	* 1x mini-PCIe slot
	* 8-pin programming header

Eliminate the extraneous headers included in PlatformGnbPcie.

BiosCallOuts normally has a bunch of extraneous references to the
mainboard name.  Rather than correct the spelling of a bunch of
instances, just get rid of them.

For the most part, use the Olive Hill ACPI definitions since the
DB-FT3b board ("Olive Hill+") and Olive Hill are the same board
with different processors.

Change some function prototypes for functions without parameters
to void instead of AGESA's VOID.  There are no parameters for
these functions, so there is no real reason to use VOID.

S3 and fan control are not supported.  HD audio is not working.

Change-Id: I794d7a8f4f948346cfe7cbd443c9aed5f70c99ed
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/6681
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <gaumless@gmail.com>

1 files changed, 91 insertions, 0 deletions

diff --git a/src/mainboard/amd/olivehillplus/dsdt.asl b/src/mainboard/amd/olivehillplus/dsdt.asl
new file mode 100644
index 0000000000..15bcd3dfa4
--- /dev/null
+++ b/src/mainboard/amd/olivehillplus/dsdt.asl
@@ -0,0 +1,91 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* DefinitionBlock Statement */
+DefinitionBlock (
+	"DSDT.AML",	/* Output filename */
+	"DSDT",		/* Signature */
+	0x02,		/* DSDT Revision, needs to be 2 for 64bit */
+	"AMD   ",	/* OEMID */
+	"COREBOOT",	/* TABLE ID */
+	0x00010001	/* OEM Revision */
+	)
+{	/* Start of ASL file */
+	/* #include <arch/x86/acpi/debug.asl> */	/* Include global debug methods if needed */
+
+	/* Globals for the platform */
+	#include "acpi/mainboard.asl"
+
+	/* Describe the USB Overcurrent pins */
+	#include "acpi/usb_oc.asl"
+
+	/* PCI IRQ mapping for the Southbridge */
+	#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
+
+	/* Describe the processor tree (\_PR) */
+	#include <cpu/amd/agesa/00730F01/acpi/cpu.asl>
+
+	/* Contains the supported sleep states for this chipset */
+	#include <southbridge/amd/agesa/hudson/acpi/sleepstates.asl>
+
+	/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
+	#include "acpi/sleep.asl"
+
+	/* System Bus */
+	Scope(\_SB) { /* Start \_SB scope */
+	 	/* global utility methods expected within the \_SB scope */
+		#include <arch/x86/acpi/globutil.asl>
+
+		/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
+		#include "acpi/routing.asl"
+
+		Device(PWRB) {
+			Name(_HID, EISAID("PNP0C0C"))
+			Name(_UID, 0xAA)
+			Name(_PRW, Package () {3, 0x04})
+			Name(_STA, 0x0B)
+		}
+
+		Device(PCI0) {
+			/* Describe the AMD Northbridge */
+			#include <northbridge/amd/agesa/00730F01/acpi/northbridge.asl>
+
+			/* Describe the AMD Fusion Controller Hub Southbridge */
+			#include <southbridge/amd/agesa/hudson/acpi/fch.asl>
+		}
+
+		/* Describe PCI INT[A-H] for the Southbridge */
+		#include <southbridge/amd/agesa/hudson/acpi/pci_int.asl>
+
+	} /* End \_SB scope */
+
+	/* Describe SMBUS for the Southbridge */
+	#include <southbridge/amd/agesa/hudson/acpi/smbus.asl>
+
+	/* Define the General Purpose Events for the platform */
+	#include "acpi/gpe.asl"
+
+	/* Define the Thermal zones and methods for the platform */
+	#include "acpi/thermal.asl"
+
+	/* Define the System Indicators for the platform */
+	#include "acpi/si.asl"
+}
+/* End of ASL file */